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G65SC802 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 G65SC802
기능 CMOS 8/16-BIT MICROPROCESSOR
제조업체 California Micro Devices Corp
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G65SC802 데이터시트 및 G65SC802 PDF

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G65SC802 pdf, 반도체, 판매, 대치품
Timing Diagram (G65SC816)
Timing Notes:
1. Typical output load = 100 pF
2. Voltage levels are Vl < 0.4V, Vh > 2.4V
3. Timing measurement points are 0.8V and 2.0V
Functional Description
The G65SC802 offers the design engineer the opportunity to utilize both
existing software programs and hardware configurations, while also
achieving the added advantages of increased register lengths and faster
execution times. The G65SC802’s “ease of use” design and implementa­
tion features provide the designer with increased flexibility and reduced
implementation costs. In the Emulation mode, the G65SC802 not only
offers software compatibility, but is also hardware (pin-to-pin) com­
patible with 6502 designs.. . plus it provides the advantages of 16-bit
internal operation in 6502-compatible applications. The G65SC802 is an
excellent direct replacement microprocessor for 6502 designs.
The G65SC816 provides the design engineer with upward mobility and
software compatibility in applications where a 16-bit system configura­
tion is desired. The G65SC816’s 16-bit hardware configuration, coupled
with current software allows a wide selection of system applications. In
the Emulation mode, the G65SC816 offers many advantages, including
full software compatibility with 6502 coding. In addition, the G65SC816’s
powerful instruction set and addressing modes make it an excellent
choice for new 16-bit designs.
Internal organization of the G65SC802 and G65SC816 can be divided
into two parts: 1) The Register Section, and 2) The Control Section. In­
structions (or opcodes) obtained from program memory are executed
by implementing a series of data transfers within the Register Section.
Signals that cause data transfers to be executed are generated within the
Control Section. Both the G65SC802 and the G65SC816 have a 16-bit
internal architecture with an 8-bit external data bus.
Instruction Register and Decode
An opcode enters the processor on the Data Bus, and is latched into the
Instruction Register during the instruction fetch cycle. This instruction is
then decoded, along with timing and interrupt signals, to generate the
various Instruction Register control signals.
Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is ex­
ecuted. The TCU is set to zero each time an instruction fetch is executed,
and is advanced at the beginning of each cycle for as many cycles as is
required to complete the instruction. Each data transfer between regis­
ters depends upon decoding the contents of both the Instruction Regis­
ter and the Timing Control Unit.
Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the 16-bit ALU. In
addition to data operations, the ALU also calculates the effective address
for relative and indexed addressing modes. The result of a data operation
is stored in either memory or an internal register. Carry, Negative, Over­
flow and Zero flags may be updated following the ALU data operation.
Internal Registers (Refer to Figure 2, Programming Model)
Accumulator (A)
The Accumulator is a general purpose register which stores one of the
operands, or the result of most arithmetic and logical operations. In the
Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the
Accumulator is established as 16 bits wide. When the Accumulator Select
Bit (M) equals one, the Accumulator is 8 bits wide. In this case, the upper
8 bits (AH) may be used for temporary storage in conjunction with the
Swap Accumulator (SWA) instruction.
Data Bank (DB)
During the Native mode (E=0), the 8-bit Data Bank Register holds the
default bank address for memory transfers. The 24-bit address is com­
posed of the 16-bit instruction effective address and the 8-bit Data Bank
address. The register value is multiplexed with the data value and is pres­
ent on the Data/Address lines during the first half of a data transfer mem­
ory cycle for the G65SC816. The Data Bank Register is initialized to zero
during Reset.
Direct (D)
The 16-bit Direct Register provides an address offset for all instructions
using direct addressing. The effective bank zero address is formed by
adding the 8-bit instruction operand address to the Direct Register. The
Direct Register is initialized to zero during Reset.

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G65SC802 전자부품, 판매, 대치품
Valid Data Address (VDA) and
Valid Program Address (VPA)—G65SC816
These two output signals indicate the type of memory being accessed by
the address bus. The following coding applies:
VDA VPA
0 0 Internal Operation—Address and Data Bus available.
0 1 Valid program address—may be used for program cache
control.
1 0 Valid data address—may be used for data cache control.
1 1 Opcode fetch—may be used for program cache control
and single step control.
Vdd and Vss
Vdd is the positive supply voltage and Vss is system logic ground. Either
of the two Vss pins on the G65SC802 may be used for system ground.
Vector Pull (VP)—G65SC816
The Vector Pull output indicates that a vector location is being addressed
during an interrupt sequence. VP is low during the last two interrupt
sequence cycles, during which time the processor reads the interrupt
vector. TheW signal may be used to select and prioritize interrupts from
several sources by modifying the vector addresses.
8 BITS 8 BITS 8 BITS
DB DB DATA BANK REGISTER
XH XL INDEX REGISTER (X)
YH YL INDEX REGISTER (Y)
* 00 SH SL STACK POINTER (S)
AH AL ACCUMULATOR (A)
PB
PCH
PCL
PROGRAM COUNTER (PC)
PROGRAM BANK REGISTER (PB)
00 DH DL DIRECT REGISTER (D)
L = LOW, H = HIGH
ALWAYS 1 IF E = 1
BREAK
‘ 0 ON STACK AFTER INTERRUPT IF E = 1
1 E3
n EMULATION BIT
E
0 = NATIVE MODE
1 = 6502 EMULATION
PROCESSOR STATUS REGISTER (P)
N V M )( D 1 Z C
n CARRY
1 = TRUE
ZERO
1 = RESULT ZERO
IRQ DISABLE
1 = DISABLE
DECIMAL MODE
1 = DECIMAL MODE
INDEX REG. SELECT 1 = 8 BIT, 0 = 16 BIT
MEMORY/ACC. SELECT 1 = 8 BIT, 0 = 16 BIT
OVERFLOW
TRUE
NEGATIVE
NEGATIVE
Figure 2. Programming Model
%
Table 1. G65SC802 and G65SC816 Compatibility
Function
Decimal Mode:
• After Interrupts
• N, Z Flags
• ADC, SBC
Read-Modify-Write:
• Absolute Indexed, No Page Crossing
• Write
• Memory Lock
Jump Indirect:
• Cycles
• Jump Address, Operand = XXFF
Branch or Index Across Page Boundary
0 — RDY During Write
Write During Reset
Unused Opcodes
01 (OUT), 02 (OUT), SO, SYNC Signals
RDY Signal
G65SC802/816 Emulation
0- D
Valid
No added cycle
7 cycles
Last 2 cycles
Last 3 cycles
5 cycles
Correct
Read last program byte
G65SC802: Ignored until read
G65SC816: Processor stops
No
No operation
Available with G65SC802 only
Bidirectional
G65SC02
0- D
Valid
Add 1 cycle
6 cycles
Last cycle
Last 2 cycles
6 cycles
Correct
Read last program byte
Processor stops
Yes
No operation
Available
Input
NMOS 6502
Not initialized
Undefined
No added cycle
7 cycles
Last 2 cycles
Not available
5 cycles
Invalid
Read invalid address
Ignored until read
No
Undefined
Available
Input
7

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