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SI7112DN 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 SI7112DN
기능 N-Channel 30 V (D-S) Fast Switching MOSFET
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SI7112DN 데이터시트 및 SI7112DN PDF

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SI7112DN pdf, 반도체, 판매, 대치품
Si7112DN
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
60 0.05
0.04
TJ = 150 °C
10
TJ = 25 °C
0.03
0.02
0.01
ID = 18.9 A
1
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
0.4
0.2
0.0
- 0.2
- 0.4
- 0.6
ID = 250 µA
50
40
30
20
10
- 0.8
- 50 - 25
0 25 50 75 100 125 150
TJ - Temperature (°C)
Threshold Voltage
0
0.01
0.1
1 10 100 600
Time (s)
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
IDM Limited
P(t) = 0.0001
10
ID(on)
1 Limited
P(t) = 0.001
P(t) = 0.01
P(t) = 0.1
0.1
TC = 25 °C
Single Pulse
P(t) = 1
P(t) = 10
DC
BVDSS Limited
0.01
0.1 1
10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
www.vishay.com
Document Number: 72864
4 S11-0855-Rev. G, 02-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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SI7112DN 전자부품, 판매, 대치품
AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
www.vishay.com
1

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SI7112DN

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