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MPC8306S 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 MPC8306S
기능 PowerQUICC II Pro Integrated Communications Processor
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MPC8306S 데이터시트 및 MPC8306S PDF

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MPC8306S pdf, 반도체, 판매, 대치품
Overview
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each
running at 64 kbps
For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference
Manual with Protocol Interworking.
• DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— 16-bit data interface, up to 266-MHz data rate
— 14 address lines
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface.
– 64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support)
– One 16-bit device or two 8-bit devices on a 16-bit bus,
— Support for up to 16 simultaneous open pages for DDR2
— One clock pair to support up to 4 DRAM devices
— Supports auto refresh
— On-the-fly power management using CKE
• Enhanced local bus controller (eLBC)
— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
— Eight chip selects supporting eight external slaves
– Four chip selects dedicated
– Four chip selects offered as multiplexed option
— Supports boot from parallel NOR Flash and parallel NAND Flash
— Supports programmable clock ratio dividers
— Up to eight-beat burst transfers
— 16- and 8-bit ports, separate LWE for each 8 bit
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
— Variable memory block sizes for FCM, GPCM, and UPM mode
— Default boot ROM chip select with configurable bus width (8 or 16)
— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC
slave devices
• Integrated programmable interrupt controller (IPIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for external and internal discrete interrupt sources
— Programmable highest priority request
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
4 Freescale Semiconductor

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MPC8306S 전자부품, 판매, 대치품
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic
Symbol
Max Value
Unit Notes
Input voltage
DDR2 DRAM signals
DDR2 DRAM reference
Local bus, DUART, SYS_CLK_IN,
system control and power
management, I2C, SPI, and JTAG
signals
MVIN
MVREF
OVIN
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD + 0.3)
–0.3 to (OVDD + 0.3)
V
V
V
3
3
4
Storage temperature range
TSTG
–55 to 150
C —
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
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MPC8306S

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