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W78E858 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W78E858
기능 8-BIT MICROCONTROLLER
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W78E858 데이터시트 및 W78E858 PDF

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W78E858 pdf, 반도체, 판매, 대치품
W78E858
3. PIN CONFIGURATIONS
T
2 AA A A
ET
DD D D
X2
01 2 3
..
.. . .
PP P P PPV PP P P
11 1 1 14D00 0 0
. . . . . . D. . . .
43 2 1 02
01 2 3
P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11
44-pin
35
12
PLCC
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P P X X VP PP P P P
3 3 T T S4 2 2 2 2 2
. . A A S. . . . . .
67 LL
0 01 2 3 4
, , 21
,, , , ,
//
AA A A A
WR
89 1 1 1
RD
012
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
W R, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 40-pin 32
10 DIP 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
VCC
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
T
2 AA A A
ET
DD D D
X2
01 2 3
.
P PP P
1 11 1
. .. .
4 32 1
. ..
PP
PP
14 V 0 0
. . D. .
02 D0 1
..
PP
00
..
23
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6
44-pin PQFP
28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P P X X VP P P P P P
3 3 T T S4 2 2 2 2 2
. . A A S. . . . . .
67 LL
0 01 2 3 4
, , 21
,, , , ,
//
AA A A A
WR
89 1 1 1
RD
0 12
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
Publication Release Date: April 22, 2008
- 4 - Revision A8

4페이지

W78E858 전자부품, 판매, 대치품
W78E858
5.2.3 Software Protected Data Write
The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme
is enabled, any write operation requires a series of three-byte program commands (with specific data
to a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up or power-down. Once enabled, the software data protection will remain
enabled unless the disable commands are issued. To reset the device to unprotected mode, a six-byte
command sequence is required.
The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM
flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The
data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.
5.2.4 Command Codes for Software Data Protection Enable/Disable and Software Erase
BYTE
SEQUENCE
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
ENABLE WRITE PROTECT
ADDRESS
DATA
FFD5H
AAH
FFAAH
55H
FFD5H
A0H
--
--
--
DISABLE WRITE PROTECT
ADDRESS
DATA
FFD5H
AAH
FFAAH
55H
FFD5H
80H
FFD5H
AAH
FFAAH
55H
FFD5H
20H
SOFTWARE ERASE
ADDRESS
DATA
FFD5H
AAH
FFAAH
55H
FFD5H
80H
FFD5H
AAH
FFAAH
55H
FFD5H
10H
Auiliary RAM 512 Bytes
External Memory
0000H
01FFH
0200H
5.3 Demo Code:
EEPROM_BASE EQU
EEPROM 128 Bytes
(a) Standard 51 Series
FF80H
FFFFH
Fig. On-Chip External Memory Addressed Mapping
FF80H
Publication Release Date: April 22, 2008
- 7 - Revision A8

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W78E858

The functions of this components is a 8-BIT MICROCONTROLLER.

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The functions of this components is a 8-BIT MICROCONTROLLER.

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