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W79E632A 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W79E632A
기능 8-BIT MICROCONTROLLER
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W79E632A 데이터시트 및 W79E632A PDF

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W79E632A pdf, 반도체, 판매, 대치품
W79E632A/W79L632A
4. PIN DESCRIPTION
SYMBOL TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
EA
I external ROM. It should be kept high to access internal ROM. The ROM address
and data will not be present on the bus if EA pin is high and the program
counter is within 128 KB area. Otherwise they will be present on the bus.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O Port 0 address/data bus during fetch and MOVC operations. When internal ROM
access is performed, no PSEN strobe signal outputs from this pin.
ALE
O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: Ground potential
VDD I POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
P0.0 P0.7 I/O multiplexed low order address/data bus during accesses to external memory.
Port 0 has internal pull-up resisters enabled by software.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
P1.0 P1.7 I/O T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
P2.0 P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0) : Serial Port 0 input
TXD(P3.1) : Serial Port 0 output
INT0 (P3.2) : External Interrupt 0
P3.0 P3.7 I/O INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Port 4 is a 4-bit bi-directional I/O port. The P4.3 also provides the
P4.0 P4.3 I/O
alternate function REBOOT which is H/W reboot from LD flash.
* Note: TYPE I : input, O: output, I/O: bi-directional.
-4-

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W79E632A 전자부품, 판매, 대치품
W79E632A/W79L632A
6. MEMORY ORGANIZATION
The W79E(L)632 separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used
to store data or for memory mapped devices.
Program Memory
The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. By invoking the
banking methodology, W79E(L)632 can extend to two 64KB flash EPROM banks, APFlash0 and
APFlash1. There are on-chip ROM banks which can be used similarly to that of the 8052. All instructions
are fetched for execution from this memory area. The MOVC instruction can also access this memory
region. There is an auxiliary 4KB Flash EPROM bank (LDFlash) resided user loader program for In-
System Programming (ISP). Both APFlashs allow serial or parallel download according to user loader
program in LDFlash.
Data Memory
The W79E(L)632 can access up to 64Kbytes of external Data Memory. This memory region is accessed
by the MOVX instructions. Unlike the 8051 derivatives, the W79E(L)632 contains on-chip 1K bytes
MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions. These 1K bytes of
SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is optional under
software control. When enabled by software, any MOVX instruction that uses this area will go to the on-
chip RAM. MOVX addresses greater than 03FFH automatically go to external memory through Port 0
and 2. When disabled, the 1KB memory area is transparent to the system memory map. Any MOVX
directed to the space between 0000H and FFFFH goes to the expanded bus on Port 0 and 2. This is the
default condition. In addition, the W79E(L)632 has the standard 256 bytes of on-chip Scratchpad RAM.
This can be accessed either by direct addressing or by indirect addressing. There are also some Special
Function Registers (SFRs), which can only be accessed by direct addressing. Since the Scratchpad
RAM is only 256 bytes, it can be used only when data contents are small. In the event that larger data
contents are present, two selections can be used. One is on-chip MOVX SRAM, the other is the external
Data Memory. The on-chip MOVX SRAM can only be accessed by a MOVX instruction, the same as that
for external Data Memory. However, the on-chip RAM has the fastest access times.
Publication Release Date: Nov. 11, 2009
- 7 - Revision A10

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