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W78C54 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W78C54
기능 8-BIT MICROCONTROLLER
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W78C54 데이터시트 및 W78C54 PDF

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W78C54 pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
W78C54
P1.0
~
P1.7
Port
1
Port 1
Latch
INT2
INT3
Interrupt
Timer
2
Timer
0
Timer
1
UART
P3.0
~
P3.7
Port
3
Port 3
Latch
ACC
T1
B
T2
PSW
ALU
Stack
Pointer
Instruction
Decoder
&
Sequencer
SFR RAM
Address
256 bytes
RAM & SFR
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
16KB
ROM
P4.0
~
P4.3
Port
4
Port 4
Latch
Bus & Clock
Controller
Port 2
Latch
Oscillator
Reset Block Power control
XTAL1 XTAL2 ALE PSEN RST
VCC GND
P0.0
Port
0
~
P0.7
P2.0
Port ~
2 P2.7
Figure 2. Architecture of the W78C54
-4-

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W78C54 전자부품, 판매, 대치품
W78C54
DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS)
SYM.
B
ACC
P4*
DEFINITION
B register
Accumulator
Port 4
PSW
Program status word
TH2 T2 reg. high
TL2 T2 reg. low
RCAP2H T2 capture high
RCAP2L T2 capture low
T2CON Timer 2 control
XICON* External interrupt
control
IP Interrupt priority
P3 Port 3
IE Interrupt enable
P2 Port 2
SBUF
SCON*
Serial buffer
Serial control
P1* Port 1
AUXR*
TH1
TH0
TL1
TL0
TMOD
TCON
Auxiliary
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
Timer control
PCON*
DPH
DPL
SP
P0
Power control
Data pointer high
Data pointer low
Stack pointer
Port 0
ADDR.
MSB
BIT ADDRESS, SYMBOL
F0H (F7) (F6) (F5) (F4) (F3) (F2)
E0H (E7) (E6) (E5) (E4) (E3) (E2)
D8H
-
-
-
- (DB) (DA)
INT2 INT3
D0H (D7) (D6) (D5) (D4) (D3) (D2)
CY AC F0 RS1 RS0 OV
CDH
CCH
CBH
CAH
C8H (CF) (CE) (CD) (CC) (CB) (CA)
TF2 EXF2 RCLK TCLK EXEN2 TR2
C0H (C7) (C6) (C5) (C4) (C3) (C2)
PX3 EX3 IE3 IT3 PX2 EX2
B8H -
- PT2 PS PT1 PX1
B0H (B7) (B6) (B5) (B4) (B3) (B2)
RD WR T1
T0 INT1 INT0
A8H (AF) (AE) (AD) (AC) (AB) (AA)
EA - ET2 ES ET1 EX1
A0H (A7) (A6) (A5) (A4) (A3) (A2)
A15 A14
99H
98H (9F) (9E)
SM0/FE SM1
90H (97) (96)
A13
(9D)
SM2
(95)
A12
(9C)
REN
(94)
A11
(9B)
TB8
(93)
A10
(9A)
RB8
(92)
8EH
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
--
GATE C/T
(8F) (8E)
TF1 TR1
SMOD SMOD0
(87) (86)
-
M1
(8D)
TF0
-
(85)
--
M0 GATE
(8C) (8B)
TR0 IE1
POF+ GF1
(84) (83)
-
C/T
(8A)
IT1
GF0
(82)
(F1)
(E1)
(D9)
LSB
(F0)
(E0)
(D8)
RESET
00000000B
00000000B
xxxx0000B
(D1) (D0) 00000000B
-P
00000000B
00000000B
00000000B
00000000B
(C9) (C8) 00000000B
C/T2 CP/RL2
(C1) (C0) 00000000B
IE2 IT2
PT0 PX0 xx000000B
(B1) (B0) 11111111B
TXD RXD
(A9) (A8) 00000000B
ET0 EX0
(A1) (A0) 11111111B
A9 A8
xxxxxxxxB
(99) (98) 00000000B
TI RI
(91) (90) 11111111B
T2EX T2
- AO xxxxxxx0B
00000000B
00000000B
00000000B
00000000B
M1 M0 00000000B
(89) (88) 00000000B
IE0 IT0
PD IDL 00xxxx00B
00000000B
00000000B
00000111B
(81) (80) 11111111B
Publication Release Date: December 1997
- 7 - Revision A2

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