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W79E658A 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W79E658A
기능 8-BIT MICROCONTROLLER
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W79E658A 데이터시트 및 W79E658A PDF

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W79E658A pdf, 반도체, 판매, 대치품
W79E658A/W79L658A
1. General Description
The W79E658 is a fast, 8051/52-compatible microcontroller with a redesigned processor core that
eliminates wasted clock and memory cycles. Typically, the W79E658 executes instructions 1.5 to 3
times faster than that of the traditional 8051/52, depending on the type of instruction, and the overall
performance is about 2.5 times better at the same crystal speed. As a result, with the fully-static
CMOS design, the W79E658 can accomplish the same throughput with a lower clock speed, reducing
power consumption.
The W79E658 provides 256 bytes of on-chip RAM; 1-KB of auxiliary RAM; seven 8-bit, bi-directional
and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; an UART serial
port, 2 channels of I2C with master/slave capability and 8 channels of 10-bit ADC. These peripherals
are all supported by ten interrupt sources with 2 levels of priority.
The W79E658 contains a 128-KB Flash EPROM whose contents may be updated in-system by a
loader program stored in an auxiliary, 4-KB Flash EPROM. Once the contents are confirmed, it can be
protected for security.
Note: If the applied VDD is not stable, especially with long transition time of power on/off, it’s
recommended to apply an external RESET IC to the RST pin for improving the stability of
system.
2. Features
Fully-static-design 8-bit Turbo 51 CMOS microcontroller up to 40MHz
128-KB of in-system-programmable Flash EPROM (AP Flash EPROM with ISP)
4-KB of Auxiliary Flash EPROM for the loader program (LD Flash EPROM)
1-KB auxiliary RAM, software-selectable, accessed by MOVX instruction
256 bytes of scratch-pad RAM
Seven 8-bit bi-directional ports
All pins with Schmitt trigger inputs
One 4-bit multipurpose I/O port4 with Chips select(CS) and boot function
Three 16-bit timers
6 channels of 8-bit PWM
One enhanced full-duplex UART with framing-error detection and automatic address recognition
2-channels of I2C with master/slave capability
10-bit ADC with 8-channel inputs
Software programmable access cycle to external RAM/peripherals
10 interrupt sources with two levels of priority
Software reset function
Optional H/L state of ALE/PSEN during power down mode
Built-in power management
Code protection
Development tool
JTAG ICE(In Circuit Emulator) tool
Packages:
Lead Free(RoHS) QFP 100:
W79E658A40FL, W79L658A25FL
-4-

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W79E658A 전자부품, 판매, 대치품
W79E658A/W79L658A
PIN DESCRIPTION, continued
SYMBOL TYPE
DESCRIPTIONS
I/O
P4.0P4.3 S H
PORT 4: 4-bit bi-directional I/O port. The P4.3 also provides the alternate
function REBOOT which is H/W reboot from LD flash.
P5.0-P5.7
I/O H
PORT 5: A bi-directional I/O port with internal pull-ups. This port is not bit-
addressable. The alternate functions of P5.0 to P5.3 are inputs of ADC4 to
ADC7.
P6.0-P6.7
I/O
DH
PORT 6: A bi-directional I/O port with internal pull-ups. This port is not bit-
addressable. Pins P6.4 to P6.7 are open drain type and can be software
configured as the I2C ports.
P7.0-P7.7
TCK2
TMS2
TDI2
TDO2
TRST2
I/O H
IH
IH
IH
OL
IH
PORT 7: A bi-directional I/O port with internal pull-ups. This port is not bit-
addressable.
Used in debug mode with internal pull-up
Used in debug mode with internal pull-up
Used in debug mode with internal pull-up
Used in debug mode with internal weakly pull-low
Used in debug mode with internal pull-up
Note:
1. TYPE I : input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain S: Schmitt Trigger
2. Keep debug pins in NC(no connection) if chip is not in debug mode.
4.1 Port 4
SFR P4 at address A5H, is a 4-bit multipurpose programmable I/O port which functions are I/O, insert
wait function and chip-select function. The Port 4 has four different operation modes:
In mode 0, P4.0 ~ P4.3 is a 4-bit bi-directional I/O port which is the same as port 1. The default Port 4
is a general I/O function.
In mode1, P4.0 ~ P4.3 are read data strobe signals which are synchronized with RD signal at specified
addresses. These read data strobe signals can be used as chip-select signals for external peripherals.
In mode2, P4.0 ~ P4.3 are write data strobe signals which are synchronized with WR signal at
specified addresses. These write data strobe signals can be used as chip-select signals for external
peripherals.
In mode3, P4.0 ~ P4.3 are read/write data strobe signals which are synchronized with RD
or WR signal at specified addresses. These read/write data strobe signals can be used as chip-select
signals for external peripherals.
In mode1~mode3, Port 4 is configured with the feature of chip-select signals, the address range for
chip-select signals depends on the contents of registers P4xAH and P4xAL, which contain the high-
order byte and low-order byte, respectively, of the 16-bit address comparator for P4.x. The registers
P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode. This is
illustrated in the following schematic.
Publication Release Date: Oct 08, 2010
- 7 - Revision A5.0

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W79E658A

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