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W78C32C 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W78C32C
기능 8-BIT MICROCONTROLLER
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W78C32C 데이터시트 및 W78C32C PDF

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W78C32C pdf, 반도체, 판매, 대치품
W78C32C
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
RAM
256
Bytes
CPU
CORE
SFR
Data Bus
Interrupt
Timer 2
Serial
Port
Timer 0
Timer 1
INT 0
INT 1
Port 0
Port 1
Alternate
Port 2
Port 3
Alternate
-4-

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W78C32C 전자부품, 판매, 대치품
W78C32C
DC Characteristics, continued
PARAMETER
SYM. TEST CONDITIONS
Output High Voltage
P1, P3
VOH1 VDD = 4.5V
IOH1 = -100 µA
Output High Voltage
ALE, PSEN , P0 (*1), P2 (*1)
VOH2 VDD = 4.5V
IOH2 = -400 µA
Input Low Voltage
P1, P3
VIL1 VDD = 4.5V
Input Low Voltage
XTAL1, RST (*3)
VIL2 VDD = 4.5V
Input High Voltage
P1, P3
VIH1 VDD = 5.5V
Input High Voltage
XTAL1, RST (*3)
VIH2 VDD = 5.5V
Notes:
1. P0 and P2 are in external access mode.
2. RST pin has an internal pull-down resistor of about 30K .
3. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
SPECIFICATION
MIN. TYP. MAX.
2.4 -
-
UNIT
V
2.4 -
-V
0-
0.8 V
0-
0.8 V
2.4 - VDD +0.2 V
3.5 - VDD +0.2 V
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
F OP, TCP
PARAMETER
SYMBOL
MIN.
Operating Speed
FOP
0
Clock Period
TCP 25
Clock High
TCH
10
Clock Low
TCL 10
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
-7-
TYP.
-
-
-
-
MAX.
40
-
-
-
UNIT
MHz
nS
nS
nS
NOTES
1
2
3
3
Publication Release Date: July 1999
Revision A2

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