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W77E532A 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 W77E532A
기능 8-BIT MICROCONTROLLER
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W77E532A 데이터시트 및 W77E532A PDF

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W77E532A pdf, 반도체, 판매, 대치품
W77E532/W77E532A
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
I external ROM. It should be kept high to access internal ROM. The ROM address
and data will not be present on the bus if EA pin is high.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O Port 0 address/data bus during fetch and MOVC operations. When internal ROM
access is performed, no PSEN strobe signal outputs from this pin.
ALE
O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: Ground potential
VDD I POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
P0.0 P0.7 I/O multiplexed low order address/data bus during accesses to external memory.
Port 0 has internal pull-up resisters enabled by software.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 2 RXD
P1.0 P1.7 I/O TXD1(P1.3): Serial port 2 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
P2.0 P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
Publication Release Date: June 30, 2009
- 4 - Revision A10

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W77E532A 전자부품, 판매, 대치품
W77E532/W77E532A
Timers
The W77E532A has three 16-bit timers that are functionally similar to the timers of the 8052 family.
When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing
the user with the option of operating in a mode that emulates the timing of the original 8052. The
W77E532A has an additional feature, the watchdog timer. This timer is used as a System Monitor or as
a very long time period timer.
Interrupts
The Interrupt structure in the W77E532A is slightly different from that of the standard 8052. Due to the
presence of additional features and peripherals, the number of interrupt sources and vectors has been
increased. The W77E532A provides 12 interrupt resources with two priority level, including six external
interrupt sources, timer interrupts, serial I/O interrupts.
Data Pointers
The original 8052 had only one 16-bit Data Pointer (DPL, DPH). In the W77E532A, there is an
additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which
were unused in the original 8052. In addition there is an added instruction, DEC DPTR (op-code A5H),
which helps in improving programming flexibility for the user.
Power Management
Like the standard 80C52, the W77E532A also has IDLE and POWER DOWN modes of operation. The
W77E532A provides a new Economy mode which allow user to switch the internal clock rate divided by
either 4, 64 or 1024. In the IDLE mode, the clock to the CPU core is stopped while the timers, serial
ports and interrupts clock continue to operate. In the POWER DOWN mode, all the clock are stopped
and the chip operation is completely stopped. This is the lowest power consumption state.
On-chip Data SRAM
The W77E532A has 1K Bytes of data space SRAM which is read/write accessible and is memory
mapped. This on-chip MOVX SRAM is reached by the MOVX instruction. It is not used for executable
program memory. There is no conflict or overlap among the 256 bytes Scratchpad RAM and the 1K
Bytes MOVX SRAM as they use different addressing modes and separate instructions. The on-chip
MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After a reset, the DME0 bit is
cleared such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H FFFFH
access to the external memory.
Publication Release Date: June 30, 2009
- 7 - Revision A10

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