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ADV7481 데이터시트 PDF


ADV7481 Datasheet : 부품 기능 및 핀배열 알아보기

부품번호 ADV7481
기능 Integrated Video Decoder and Dual Mode HDMI/MHL Receiver
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ADV7481 데이터시트 및 ADV7481 PDF

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ADV7481 pdf, 반도체, 판매, 대치품
ADV7481
DETAILED FUNCTIONAL BLOCK DIAGRAM
Data Sheet
SCLK
SDATA
ALSB
RESET
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI_CS
VBUS_EN
CD_SENSE
HPD/CBUS
RX_5V/VBUS
CEC
DDC_SDA
DDC_SCL/
CD_PULLUP
RXCP/RXCN
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
LLC
P0
P1
P2
P3
P4
P5
P6
P7
XTALP
XTALN
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
DIAG1
DIAG2
DIAG3
DIAG4
I2C SLAVE/
CONTROL
SPI
SLAVE
CBUS
CONTROLLER
MHL LINK
DISCOVERY
BLOCK
5V DETECT AND
HPD PIN
CONTROLLER
CEC
CONTROLLER
HDCP
KEYS
HDCP
ENGINE
EDID/
REPEATER
CONTROLLER
ADV7481
GENERAL
INTERRUPTS
CONTROLLER
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
AUDIO
PROCESSOR
CBUS
INTERRUPTS
CONTROLLER
AUDIO OUTPUT
FORMATTER
PLL
EQUALIZER
SAMPLER
HDMI/MHL
PROCESSOR
COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
(CP)
8-BIT
DIGITAL
INPUT/
OUTPUT
PORT
CLOCK PROCESSING BLOCK
PLL ADLLT PROCESSING
8-BIT
TO
6-BIT
DITHER
BLOCK
MIPI CSI-2
TRANSMITTER A
CSI-2 Tx D-PHY Tx
INTRQ1
INTRQ2
INTRQ3
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
CLKAP/CLKAN
DA0P/DA0N
DA1P/DA1N
DA2P/DA2N
DA3P/DA3N
AA
FILTER
AA
FILTER
AA
FILTER
AA
FILTER
AFE
10-BIT ADC
+
SHA
ADC
DIAGNOSTICS
REFERENCE
STANDARD DEFINITION
PROCESSOR (SDP)
2D COMB
VBI SLICER
COLOR DEMOD
STANDARD
AUTODETECTION
ACE
DOWN-
DITHER
MIPI CSI-2
TRANSMITTER B
CSI-2 Tx D-PHY Tx
CLKBP/CLKBN
DB0P/DB0N
VREFP
VREFN
Figure 2.
Rev. 0 | Page 4 of 22

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ADV7481 전자부품, 판매, 대치품
Data Sheet
ADV7481
Parameter
POWER-DOWN CURRENTS2, 5
Digital Supply
HDMI/MHL Terminator Supply
HDMI/MHL Comparator Supply
PLL Supply
MIPI Transmitters Supply
Digital Input/Output Supply
Analog Supply
Total Power Dissipation in Power-Down
Mode
Symbol
IDVDD_PD
ITVDD_PD
ICVDD_PD
IPVDD_PD
IMVDD_PD
IDVDDIO_PD
IAVDD_PD
Test Conditions/Comments
Min Typ Max Unit
0.2 mA
0.4 mA
0.1 mA
0.1 mA
0.1 mA
0.2 mA
0.1 mA
4 mW
1 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.
2 Guaranteed by lab characterization.
3 Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature.
4 Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), MoireX video pattern for analog inputs,
pseudorandom test pattern for digital inputs, and at worst-case temperature.
5 Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature.
ANALOG VIDEO SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 2.
Parameter
NONLINEAR SPECIFICATIONS1, 2
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted2
Analog Front-End Crosstalk3
Common-Mode Rejection Ratio2, 4
LOCK TIME SPECIFICATIONS
Horizontal Lock Range3
Vertical Lock Range3
Subcarrier Lock Range3
Color Lock-In Time3
Synchronization Depth Range3
Color Burst Range3
Fast Switch Speed2, 5
Symbol Test Conditions/Comments
DP CVBS input, modulated five-step
DG CVBS input, modulated five-step
LNL CVBS input, five-step
SNR Luma ramp
Luma flat field
CMRR
fSC
Min Typ Max Unit
0.9 Degrees
0.5 %
2.0 %
57.1 dB
58 dB
60 dB
73 dB
−5
40
±1.3
60
20
5
100
+5
70
200
200
%
Hz
kHz
Lines
%
%
ms
1 These specifications apply to all CVBS input types, as well as to single-ended and differential CVBS inputs.
2 Guaranteed by lab characterization.
3 Guaranteed by design.
4 The CMRR of this circuit design is critically dependent on the external resistor matching its inputs. This measurement was performed with 0.1% tolerant resistors, a
common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
5 The time it takes the ADV7481 to switch from one analog input (single ended or differential) to another, for example, switching from AIN1 to AIN2.
Rev. 0 | Page 7 of 22

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