PDF CS1112YDWF24 Data sheet ( Hoja de datos )

Número de pieza	CS1112YDWF24
Descripción	Quad Power Output Driver
Fabricantes	ON Semiconductor
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No Preview Available ! CS1112 Quad Power Output Driver The CS1112 is a Power Output Driver. The IC incorporates four protected DMOS low–side drivers designed to drive inductive and resistive loads in an automotive environment. The outputs are controlled by an 8–bit serial peripheral interface (SPI) or its associated parallel input. Each output contains overcurrent protection, open load detection, and inductive flyback clamps. The device is overvoltage protected. Overcurrent and open load faults are reported over the SPI port, and at the STATUS lead. I/O Control SPI communication is initiated by asserting CSB low. Data at the SI lead is transferred on the rising edge of SCLK. The MSB is transferred first. The outputs become active at the rising edge of CSB. Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open drain output, (STATUS) reports a fault (short to VPWR, GND, or open load) has occurred at one or more of the outputs. Protection Each output independently detects shorts to VPWR while the output is “on” and open load/short to ground while the output is “off”. The fault register will be set if a fault occurs at the output. The fault register will be reset if the fault condition is removed from the output. The fault data is latched when CSB is asserted low. If an overcurrent condition or short circuit to VBATT occurs, the output goes into a low duty cycle mode for the duration of the fault. The outputs are disabled during an overvoltage or undervoltage condition. Features • 4.0 MHz Serial Input Bus • Parallel Input Control • 1.0 Ω DMOS Drivers (typ) • Power On Reset • Internal Flyback Clamps • Status Output • Fault Protection – 46 V Peak Transient – Power Limiting – Undervoltage – Overvoltage • Fault Reporting – Open Load – Short Circuit • 8 Internally Fused Leads http://onsemi.com SO–24L DW SUFFIX CASE 751E PIN CONNECTIONS AND MARKING DIAGRAM 1 VDD VPWR OUT0 IN0 GND GND GND GND IN1 OUT1 SI CSB 24 ROSC STATUS OUT3 IN3 GND GND GND GND IN2 OUT2 SO SCLK A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping CS1112YDWF24 SO–24L 31 Units/Rail CS1112YDWFR24 SO–24L 1000 Tape & Reel © Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 10 1 Publication Order Number: CS1112/D 1 page CS1112 PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # 24 Lead SOIC 15 PIN SYMBOL OUT2 16 IN2 21 IN3 22 OUT3 23 STATUS 24 ROSC FUNCTION Open drain output three. Parallel input three. Parallel input four. Open drain output four. Open drain output, which is asserted when an open load or overcurrent condition occurs at any of the outputs. 82 kΩ resistor tied to ground to set up accurate internal cur- rent sources. CIRCUIT DESCRIPTION Typical Operation Control of the CS1112 can be done using the Serial Peripheral Interface (SPI) port using the Data Input information in Table 1, or the outputs can be controlled via the parallel inputs (IN0, IN1, IN2, IN3). IN0 controls OUT0, IN1 controls OUT1, IN2 controls OUT2, and IN3 controls OUT3. Turning the output drivers on is an OR function with the SPI input and the parallel inputs. Note: To prevent damage to the IC or the output load, VDD must be above the Power on Reset threshold (3.5 V) before IN0, IN1, IN2, or IN3 are asserted high (< 70% VDD). TIMING DIAGRAM CS SCLK SI Don’t Care OUT0 OUT1 OUT2 OUT3 Table 1. SPI Inputs D7 D6 D5 X XX MSB X = Don’t Care; MSB is Transferred first. Time D4 D3 D2 D1 D0 X OUT3 OUT2 OUT1 OUT0 LSB http://onsemi.com 5 5 Page Notes CS1112 http://onsemi.com 11 11 Page

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Número de pieza	Descripción	Fabricantes
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