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PDF CS212 Data sheet ( Hoja de datos )
| Número de pieza | CS212 | |
| Descripción | Security Detector Serial-Addressable Receiver/Transmitter | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS212
Security Detector
Serial-Addressable Receiver/Transmitter
Description
Features
The S-ART is a 16 pin circuit
designed for data transmission on a
two-lead cable. The circuit is spe-
cially developed for alarm systems
where it is desired to identify each
detector individually. There can be
up to 30 S-ART circuits/detectors
on the same 2-lead cable. This cable
transmits both DC supply to the
S-ART and information to/from the
S-ART.
The S-ART works on the principle
by which an address is sent on the
line cable and the S-ART which rec-
ognizes the address then carries out
the order which can, in principle, be
two things:
1. Transmit data from the line cable
to the S-ART's two outputs OUT0
and OUT1.
2. Answer the S-ART controller
with the condition of the 2 inputs
IN0 and IN1 or IN2-3.
The line signal is divided into 3 lev-
els in order to give a time signal for
synchronizing and a data signal
containing addresses, orders etc.
Typical signal levels for the three
levels would be 15V, 7.5V and 0V.
s Receives/Transmits Data
on Only Two Leads
s Low Current Consumption
s High Noise Immunity
s Sabotage Surveilled Loop
Input
Block Diagram
A method by
which, in principle,
the system can be
extended to an
infinite number of
S-ART is shown on
the block diagram.
The controller
scans the in/out-
puts of a number
of lines, each with
a maximum of 30
S-ARTs.
Line 1
Controller
Line N
V
CK "1"
DATA "1"
DATA "0"
S-ART
Package Options
16L PDIP & 16L SO Wide
OUT0 1
A4 2
A3 3
A2 4
A1 5
A0 6
IN1 7
IN0 8
16 OUT1
15 DSR
14 IN2
13 IN3
12 VDD
11 DATAOUT
10 Gnd
9 LINE
Rev. 4/21/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1
A Company
¨
1 page  
Functional Description
Control
Circuit
2121
2122
2123
21229
2 Wire
Transmission
Line
VCC(<14V)
Tranmission Line
10k
To Control
Bell/Det.
Etc.
N0
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DET
Loop
1mF
150
READ WORD
To check the status of a CS212's inputs: i.e., IN0 and IN1 or
IN2-3, a read word must be sent. The first 5 bits must cor-
respond to the address of the CS212 to be interrogated. Bit
#6 is the address parity bit. It must insure that the first 6
bits are an even number of "1" 's. If the parity is even and
the CS212 to be interrogated has not previously received a
parity error (odd parity), it will transmit its status, along
with an internally generated parity bit. D0 corresponds to
IN0, D1 corresponds to IN1 or IN2-3. After the address
parity bit has been transmitted the controller must pull the
line down to about 7.5V to allow the CS212 to transmit. If a
"1" is to be transmitted, no change will occur on the line. If
a "0" is to be transmitted, the CS212 will then pull the line
down. In either case, the controller must pull the line back
up to 15V in order to continue. If the CS212 has received a
parity fault, it will transmit 3 one's (D0=D1=PD=1). This
will allow the controller to detect a parity error. If a parity
error is detected by the controller, the read word must be
repeated.
Notes:
1. * Indicates IN1 & loop IN2-3 cannot be used at the same time.
2. This diagram shown CS212 circuit coded to #24.
A typical line signal from the control unit would look like
the following:
A0
A1 A2 A3 A4
PA
READ
BIT
D0
D1
PD
0 0 01 10 0 1 0 1
Transmitted
by Controller
Transmitted
by CS-212
1 0 01 1
The CS212 would decode this into clock and data.
Clock
Data
Positive Edge Strobes
Data into an Internal
Shift Resister
1 0011
The CS212 accepts addresses and commands in 10-bit word
formats. Three types of words must be generated: Sync,
Read and Write.
SYNC READ1 READ2 READ3 READ29 SYNC WRITE1 WRITE2 WRITE29
0 0 01 10 0 1 0 1
Data Parity
IN 1 Status
IN 0 Status
"0" for Read
Add Parity
A4=1 x 24 = 16
A3=1 x 23 = 8
A2=0 x 22 = 0
A1=0 x 21 = 0
A0=0 x 20 = 0
Binary = #24
TYPICAL READ WORD
Assume that device #24 is to be interrogated and the status
of IN0=1 and IN1=0.
SYNC WORD
Synchronization is obtained by providing the CS212 with 8
or more 1's followed by a "0". To prevent a false sync, it is
best to send 0 before the eight 1's. This word insures all cir-
cuits on the same line see the commands at the proper
time.
0 1 1 1 1 1 1 11 0
WRITE WORD
In order to update OUT0 and OUT1, a write word must be
sent to the CS212. The first 5 bits must correspond to the
CS212 to be updated. Bit #6 is an address parity bit. It must
insure even parity. D0 corresponds to OUT0 and D1 corre-
sponds to OUT1. An even data parity bit must be received
by the CS212. If the address and data parity are even and
the CS212 has not previously received a parity error, it will
update OUT0 and OUT1. If a parity error was received, the
CS212 will not be updated. In this case, a read word must
be sent to clear the parity fault.
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CS212.PDF ] | |
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