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CS3310 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS3310은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS3310 자료 제공

부품번호 CS3310 기능
기능 Stereo Digital Volume Control
제조업체 Cirrus Logic
로고 Cirrus Logic 로고


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CS3310 데이터시트, 핀배열, 회로
CS3310
Stereo Digital Volume Control
Features
z Complete Digital Volume Control
— 2 Independent Channels
— Serial Control
— 0.5 dB Step Size
z Wide Adjustable Range
— -95.5 dB Attenuation
— +31.5 dB Gain
z Low Distortion & Noise
— 0.001% THD+N
— 116 dB Dynamic Range
z Noise Free Level Transitions
z Channel-to-Channel Crosstalk Better Than
110 dB
Description
The CS3310 is a complete stereo digital volume control
designed specifically for audio systems. It features a 16-
bit serial interface that controls two independent, low-
distortion audio channels.
The CS3310 includes an array of well-matched resistors
and a low noise active output stage that is capable of
driving a 600 load. A total adjustable range of 127 dB,
in 0.5 dB steps, is achieved through 95.5 dB of attenua-
tion and 31.5 dB of gain.
The simple 3-wire interface provides daisy-chaining of
multiple CS3310's for multi-channel audio systems.
The device operates from ±5 V supplies and has an in-
put/output voltage range of ±3.75 V.
ORDERING INFORMATION
CS3310-KS
0° to 70° C 16-pin Plastic SOIC
CS3310-KSZ, Lead Free 0° to 70° C 16-pin Plastic SOIC
AINL 16
AGNDL 15
AGNDR 10
AINR 9
+
-
MUX
8
8
Control
Register
8
8
MUX
-
+
12 13
VA+ VA-
4
VD+
16
Serial to
Parallel
Register
14 AOUTL
8 MUTE
1 ZCEN
2 CS
3 SDATAI
7 SDATAO
6 SCLK
5
DGND
11 AOUTR
Cirrus Logic, Inc.
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
SEPTEMBER '05
DS82F1
1




CS3310 pdf, 반도체, 판매, 대치품
CS3310
RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground)
Parameter
Symbol Min
Typ
Max
Unit
DC Power Supplies:
Positive Digital
VD+
4.75
5.0
VA+
V
Positive Analog
VA+ 4.75 5.0 5.25 V
Negative Analog
VA -4.75 -5.0 -5.25 V
(VD+) - (VA+) (Note 3) - -0.3 -
0.0 V
Ambient Operating Temperature
TA 0 25 70 °C
Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the
recommended power connections.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
DC Power Supplies:
Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supply
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VD+
VA+
VA-
Iin
VIND
TA
TSTG
Min
-0.3
-0.3
0.3
-
-0.3
-55
-65
Max
Unit
(VA+)+ 0.3
6.0
-6.0
±10
(VA+) + 0.3
+125
+150
V
V
V
mA
V
°C
°C
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CS3310 전자부품, 판매, 대치품
CS3310
CS
SCLK
SDATAI
SDATAO
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
L0 = Left Channel Least Significant Bit R0 = Right Channel Least Significant Bit
L7 = Left Channel Most Significant Bit
R7 = Right Channel Most Significant Bit
SDATAI is latched internally on the rising edge of SCLK
SDATAO transitions after the falling edge of SCLK
SDATAO bits reflect the data previously loaded into the CS3310
Figure 3. Serial Port Timing
In single device operation, volume control data is loaded into the 16-bit shift register by holding
the CS pin low for sixteen SCLK pulses and then latched on the rising edge of CS. The previous
contents of the shift-register are shifted through the register and out SDATAO during the process.
Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO
of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from
a single serial data line without complex addressing schemes. Volume control data is loaded by
holding CS low for 16 x N SCLK pulses, where N is the number of devices in the chain. The 16
bits clocked into device #1 on SCLK pulses 1-16 are clocked into device #2 on SCLK pulses 17-
32. The CS3310s are simultaneously updated on the rising edge of CS following 16 x N SCLK
pulses Notice that a 47 kohm resistor is required to terminate SDATAI, as shown in Figure 4, due
to the high impedance state of SDATAO when CS is high..
DS82F1
AUDIO
SIGNAL
AUDIO
SIGNAL
3
SDATAI
SCLK 6
16 AINL
9 AINR
CS3310
CS 2
#1
AOUTL 14
SDATAO
AOUTR 11
7
47 k
3
SDATAI
SCLK 6
16 AINL
9 AINR
CS3310
CS 2
#2
14
AOUTL
SDATAO
AOUTR 11
7
CONTROLLER
Figure 4. Daisy Chaining Diagram
7

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