CS4124YN16 Datasheet PDF - Cherry Semiconductor Corporation
| Part Number | CS4124YN16 | |
| Description | High Side PWM FET Controller | |
| Manufacturers | Cherry Semiconductor Corporation | |
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CS4124
Preliminary
High Side PWM FET Controller
Description
The CS4124 is a monolithic integrat-
ed circuit designed primarily to
control the rotor speed of perma-
nent magnet, direct current (DC)
brush motors. It drives the gate of
an N channel power MOSFET or
IGBT with a user-adjustable, fixed
frequency, variable duty cycle,
pulse width modulated (PWM) sig-
nal. The CS4124 can also be used to
control other loads such as incan-
descent bulbs and solenoids.
Inductive current from the motor or
solenoid is recirculated through an
external diode.
The CS4124 accepts a DC level
input signal of 0 to 5V to control the
pulse width of the output signal.
This signal can be generated by a
potentiometer referenced to the on-
chip 5V linear regulator, or a fil-
tered 0% to 100% PWM signal also
referenced to the 5V regulator.
The IC is placed in a sleep state by
pulling the CTL lead below 0.5V. In
this mode everything on the chip is
shutdown except for the on-chip
regulator and the overall current
draw is less than 275µA. There are a
number of on-chip diagnostics that
look for potential failure modes and
can disable the external power
MOSFET.
Features
s 150mA Peak PWM Gate
Drive Output
s Patented Voltage
Compensation Circuit
s 100% Duty Cycle
Capability
s 5V, ± 3% Linear Regulator
s Low Current Sleep Mode
s Overvoltage Protection
s Boost Mode Power
Supply
s Output Inhibit
Applications Diagram
VBAT 42.5µH
1000µF
RS
1000µF 10
470µH
100µF
Input
1.5µF
10K
10nF
.01µF
CFLT .25µF
ROSC 93.1K
COSC 470pF
OUTPUT Gnd
BOOST INH
FLT IADJ
ROSC
ISENSE+
ISENSE-
COSC PMP
CTL
PGnd
VCC
SNI
VREG
RSNI
4
10K
1µF
P1
10K 100K
N1 10K
10µF
10K
10K
10K
RCS1
CCS 51
.022µF
RCS2
51
RSENSE
4m
RGATE 6
1M
MOT+
MOT-
Package Option
16 Lead PDIP
OUTPUT
BOOST
FLT
ROSC
COSC
CTL
PGnd
VCC
1
Gnd
INH
IADJ
ISENSE+
ISENSE-
PMP
SNI
VREG
Consult Factory for 16 Lead SOIC
Wide package.
Rev. 4/26/99
1195
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
A Company
®
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Application Information: continued
exceeds ILIM, an internal latch is set and the output pulls
the gate of the MOSFET low for the remainder of the oscil-
lator cycle (fault mode). At the start of the next cycle, the
latch is reset and the IC reverts back to run mode until
another fault occurs. If a number of faults occur in a given
period of time, the IC “times out” and disables the MOS-
FET for a long period of time to let it cool off. This is
accomplished by charging the CFLT capacitor each time an
over current condition occurs. If a cycle goes by with no
overcurrent fault occurring, an even smaller amount of
charge will be removed from CFLT. If enough faults occur
together, eventually CFLT will charge up to 2.4V and the
fault latch will be set. The fault latch will not be reset until
CFLT discharges to 0.6V. This action will continue indefi-
nitely if the fault persists.
The off time and on time are set by the following:
Off Time = CFLT ×
2.4V - 0.6V
4.5µA
where:
On Time = CFLT ×
2.4V - 0.6V
IAVG
IAVG = ( 295.5µA × DC ) - [4.5µA × (1 - DC )]
IAVG = ( 300µA × DC ) - 4.5µA
DC = PWM Duty Cycle
Sleep State
This device will enter into a low current mode (< 275µA)
when CTL lead is brought to less than 0.5V. All functions
are disabled in this mode, except for the regulator.
Inhibit
When the inhibit is greater than 2.5V the internal latch is
set and the external MOSFET will be turned off for the
remainder of the oscillator cycle. The latch is then reset at
the start of the next cycle.
Overvoltage Shutdown
The IC will disable the output during an overvoltage
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is 325mV (typical) of
hysteresis on the overvoltage function. There is no under-
voltage lockout. The device will shutdown gracefully once
it runs out of headroom.
Reverse Battery
The CS4124 will not survive a reverse battery condition. A
series diode is required between the battery and the VCC
lead for reverse battery.
Load Dump
A 10Ω resistor, (RS) is placed in series with VCC to limit the
current into the IC during 40V peak transient conditions.
Boost Switch Mode Power Supply
The CS4124 has an integrated boost mode power supply
which charges the gate of the external high-side MOSFET
to greater than 5V above VCC. Three leads are used for
voltage boost. They are Boost, PMP and SNI. The PMP
lead is the collector of a darlington tied NPN power tran-
sistor. This device charges the inductor during its on time.
The boost lead is the input to chip from the external reser-
voir capacitor. The SNI lead is the emitter of the power
NPN and is connected externally to the RSNI resistor.
The power supply is controlled by the oscillator. At the
start of a cycle an R-S flip flop is set the internal power
NPN transistor is turned on and energy begins to build up
in the inductor. The RSNI resistor sets the peak current of
the inductor by tripping a comparator when the voltage
across the resistor is 450mV. The flip flop is reset and the
inductor delivers its stored energy to the load. The ripple
voltage (VRIPPLE) at the Boost lead is controlled by CBOOST.
A snubber circuit, made up of a series resistor and capaci-
tor, is required to dampen the ringing of the inductor. A
value of 4Ω is recommended for RSNI.
A zener diode is needed between the boost output voltage
and the battery. This will clamp the boost lead to a speci-
fied value above the battery to prevent damage to the IC.
A 9 volt zener diode is recommended.
1199
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| Information | Total 6 Pages | |
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