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CS4205-KQ 데이터시트 PDF




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부품번호 CS4205-KQ 기능
기능 CrystalClear Audio Codec 97
제조업체 Cirrus Logic
로고 Cirrus Logic 로고


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CS4205-KQ 데이터시트, 핀배열, 회로
CS4205
CrystalClear® Audio Codec ’97 for Portable Computing
Features
! Integrated Asynchronous I2S Input Port
(ZV Port)
! Integrated High-Performance Microphone
Pre-Amplifier
! Integrated Digital Effects Processing for Bass
and Treble Response
! Digital Docking Including an I2S Output, 3
Synchronous I2S Inputs
! Performance Oriented Digital Mixer
! SRS© 3D Stereo Enhancement
! On-chip PLL for use with External Clock
Sources
! Dedicated Microphone Analog-to-Digital
Converter
! Sample Rate Converters
! S/PDIF Digital Audio Output
! AC ’97 2.1 Compliant
! PC Beep Bypass
! 20-bit Stereo Digital-to-Analog Converters
! 18-bit Stereo Analog-to-Digital Converters
! Three Analog Line-level Stereo Inputs for
LINE IN, VIDEO, and AUX
! High Quality Pseudo-Differential CD Input
! Extensive Power Management Support
! Meets or Exceeds the Microsoft® PC 99 and
PC 2001 Audio Performance Requirements
Description
The CS4205 is an AC ’97 2.1 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading CrystalClear® delta-sigma and mixed
signal technology. The CS405 is the first Cirrus AC ’97
audio codec to feature digital centric mixing and digital
effects. This advanced technology and these features
are designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk-
top, portable, and entertainment PCs.
Coupling the CS4205 with a PCI audio accelerator or
core logic supporting the AC ’97 interface implements a
cost effective, superior quality audio solution. The
CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au-
dio quality standards.
ORDERING INFO
CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
ID0#
ID1#
GPIO0/LRCLK
GPIO1/SDOUT
EAPD/SCLK
SPDO/SDO2
GPIO[2:4]/SDI[1:3]
ZSCLK,ZSDATA,ZLRCLK
AC-LINK AND AC '97
REGISTERS
TEST
PWR
MGT
AC-
LINK
AC
'97
REG
SIGNAL
PROCESSING
ENGINE
ANALOG INPUT MUX
AND OUTPUT MIXER
SRC PCM_DATA
SRC MIC_PCM_DATA
GAIN / MUTE CONTROLS
MIXER / MUX SELECTS
18 bit
ADC
(2ch)
18 bit
ADC
(1ch)
INPUT
MUX
INPUT
MIXER
Σ
GPIO
S/PDIF
SERIAL DATA PORT
ZV PORT
OUTPUT
MIXER
Σ20 bit
SRC PCM_DATA DAC
(2ch)
LINE
CD
AUX
VIDEO
MIC1
MIC2
PHONE
PC_BEEP
LINE_OUT
MONO_OUT
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS489PP4
1




CS4205-KQ pdf, 반도체, 판매, 대치품
CS4205
10.1.3 New Warm Reset .............................................................................................. 59
10.1.4 Register Reset .................................................................................................. 59
10.2 Powerdown Controls ...................................................................................................... 60
11. CLOCKING ........................................................................................................................... 62
11.1 PLL Operation (External Clock) ..................................................................................... 62
11.2 24.576 MHz Crystal Operation ....................................................................................... 62
11.3 Secondary Codec Operation .......................................................................................... 62
12. ANALOG HARDWARE DESCRIPTION ............................................................................... 64
12.1 Analog Inputs ................................................................................................................. 64
12.1.1 Line Inputs ......................................................................................................... 64
12.1.2 CD Input ............................................................................................................ 64
12.1.3 Microphone Inputs ............................................................................................. 65
12.1.4 PC Beep Input ................................................................................................... 65
12.1.5 Phone Input ....................................................................................................... 65
12.2 Analog Outputs .............................................................................................................. 65
12.2.1 Stereo Output .................................................................................................... 66
12.2.2 Mono Output ..................................................................................................... 66
12.3 Miscellaneous Analog Signals ....................................................................................... 66
12.4 Power Supplies .............................................................................................................. 66
12.5 Reference Design .......................................................................................................... 67
13. GROUNDING AND LAYOUT .............................................................................................. 68
14. PIN DESCRIPTIONS ....................................................................................................... 70
15. PARAMETER AND TERM DEFINITIONS ............................................................................ 77
16. REFERENCE DESIGN ..................................................................................................... 79
17. REFERENCES ...................................................................................................................... 80
18. PACKAGE DIMENSIONS ..................................................................................................... 81
LIST OF FIGURES
Figure 1. Power Up Timing............................................................................................................ 10
Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 10
Figure 3. Clocks ............................................................................................................................ 10
Figure 4. Data Setup and Hold...................................................................................................... 11
Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11
Figure 6. Test Mode ...................................................................................................................... 11
Figure 7. AC-link Connections....................................................................................................... 12
Figure 8. CS4205 Mixer Diagram.................................................................................................. 14
Figure 9. Digital Signal Path Overview.......................................................................................... 15
Figure 10. Analog Centric Mode.................................................................................................... 17
Figure 11. Digital Centric Mode..................................................................................................... 17
Figure 12. Host Processing Mode ................................................................................................. 17
Figure 13. Multi-Channel Mode ..................................................................................................... 17
Figure 14. AC-link Input and Output Framing................................................................................ 18
Figure 15. Serial Data Port: Six Channel Circuit ........................................................................... 54
Figure 16. Digital Docking Connection Diagram ........................................................................... 55
Figure 17. Serial Data Format 0 (I2S) ........................................................................................... 56
Figure 18. Serial Data Format 1 (Left Justified) ............................................................................ 56
Figure 19. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 56
Figure 20. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 56
Figure 21. ZV Port Format (I2S, 16-bit data)................................................................................. 57
Figure 22. S/PDIF Output.............................................................................................................. 58
Figure 23. PLL External Loop Filter............................................................................................... 62
Figure 24. External Crystal............................................................................................................ 63
4 DS489PP4

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CS4205-KQ 전자부품, 판매, 대치품
CS4205
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: Tambient = 25° C,
AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100 kΩ/
1000 pF load for Mono and Line Outputs; CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz,
18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.
Parameter
(Note 2)
Symbol Path
(Note 3)
CS4205-KQZ
Min Typ Max
Unit
Full Scale Input Voltage
Line Inputs
Mic Inputs
(10dB = 0, 20dB = 0)
Mic Inputs
(10dB = 1, 20dB = 0)
Mic Inputs
(10dB = 0, 20dB = 1)
Mic Inputs
(10dB = 1, 20dB = 1)
Full Scale Output Voltage
Line and Mono Outputs
Frequency Response
(Note 4)
Analog
Ac = ± 0.25 dB
DAC
Ac = ± 0.25 dB
ADC
Ac = ± 0.25 dB
FR
A-D 0.91 1.00
A-D 0.91 1.00
A-D 0.283 0.315
A-D 0.091 0.10
A-D 0.0283 0.0315
-
-
-
-
-
VRMS
VRMS
VRMS
VRMS
VRMS
D-A 0.91
1.0
1.13
VRMS
A-A 20
D-A 20
A-D 20
-
20,000
Hz
-
20,000
Hz
-
20,000
Hz
Dynamic Range
Stereo Analog Inputs to LINE_OUT
Mono Analog Input to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range
DR
A-A
A-A
D-A
A-D
90
85
85
85
95
90
90
90
- dB FS A
- dB FS A
- dB FS A
- dB FS A
DAC SNR
SNR
(-20 dB FS input w/ CCIR-RMS filter on output)
D-A - 70 - dB
Total Harmonic Distortion + Noise
THD+N
(-3 dB FS input signal):
Line Output
A-A - -90 -80 dB FS
DAC
D-A - -87 -80 dB FS
ADC
(all inputs)
A-D - -84 -80 dB FS
Power Supply Rejection Ratio
(1 kHz, 0.5 VRMS w/ 5 V DC offset)
(Note 4)
40 60 - dB
Interchannel Isolation
70 87 - dB
Spurious Tone
(Note 4)
- -100 - dB FS
Input Impedance
(Note 4)
10 -
- k
Notes: 1. ZAL refers to the analog output pin loading and CDL refers to the digital output pin loading.
2. Parameter definitions are given in Section 15, Parameter and Term Definitions.
3. Path refers to the signal path used to generate this data. These paths are defined in Section 15,
Parameter and Term Definitions.
4. This specification is guaranteed by silicon characterization; it is not production tested.
DS489PP4
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관련 데이터시트

부품번호상세설명 및 기능제조사
CS4205-KQ

CrystalClear Audio Codec 97

Cirrus Logic
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CS4205-KQZ

CrystalClear Audio Codec 97

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