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PDF CS4215-KL Data sheet ( Hoja de datos )
| Número de pieza | CS4215-KL | |
| Descripción | 16-Bit Multimedia Audio Codec | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Semiconductor Corporation
CS4215
16-Bit Multimedia Audio Codec
Features
General Description
• Sample Frequencies from 4 kHz to 50 kHz
• 16-bit Linear, 8-bit Linear, µ-Law, or A-Law
Audio Data Coding
• Programmable Gain for Analog Inputs
• Programmable Attenuation for Analog
Outputs
• On-chip Oscillators
• +5V Power Supply
• Microphone and Line Level Analog Inputs
• Headphone, Speaker, and Line Outputs
• On-chip Anti-Aliasing/Smoothing Filters
• Serial Digital Interface
The CS4215 is an MwaveTM
audio codec.
The CS4215 is a single-chip, stereo, CMOS multime-
dia codec that supports CD-quality music,
FM radio-quality music, telephone-quality speech, and
modems. The analog-to-digital and digital-to-analog
converters are 64×oversampled delta-sigma converters
with on-chip filters which adapt to the sample fre-
quency selected.
The +5V only power requirement makes the CS4215
ideal for use in workstations and personal computers.
Integration of microphone and line level inputs, input
and output gain setting, along with headphone and
monitor speaker driver, results in a very small footprint.
Ordering Information:
CS4215-KL
0°C to 70°C
CS4215-KQ
0°C to 70°C
CDB4215
Evaluation Board
44-pin PLCC
100-pin TQFP
CMOUT
LINL
LINR
MINL
MINR
SDIN
CLKIN
CLKOUT
XTL1IN
XTL1OUT
XTL2IN
XTL2OUT
PIO0
PIO1
D/C
RESET
PDN
A/D
M
U Gain
X
A/D
unsigned
µ-law
A-law
encode
Serial Input/Output
SDOUT
SCLK
FSYNC
TSIN
TSOUT
Clock
Generator
8
Monitor
Attenuator
Voltage
Reference
VREF
MOUT1
MOUT2
Control
Interface and
Registers
unsigned
µ-law
A-law
decode
+
+
D/A LOUTR
Output
LOUTL
Attenuator Mute HEADC
HEADR
D/A HEADL
VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2
This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and
previous versions, see Appendix A.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
SEPT ’93
DS76F2
1
1 page  
CS4215
SWITCHING CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = +5V,
outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Parameter
Symbol Min Typ Max Units
SCLK period
Master Mode, XCLK = 1 (Note 8) tsckw
Slave Mode (XCLK = 0) tsckw
- 1/(Fs*bpf)
80 -
-
-
s
ns
SCLK high time
Slave Mode, XCLK = 0 (Note 9) tsckh
25
-
- ns
SCLK low time
Slave Mode, XCLK = 0 (Note 9) tsckl
25
-
- ns
Input Setup Time
Input Hold Time
Input Transition Time
ts1 15
-
- ns
th1 10
-
- ns
10% to 90% points
- - 10 ns
Output delay
tpd1 -
- 28 ns
SCLK to TSOUT
tpd2 -
- 30 ns
Output to Hi-Z state
Output to non-Hi-Z
Input Clock Frequency
Timeslot 8, bit 0
Timeslot 1, bit 7
Crystals
CLKIN (Note 10)
thz
tnz
-
15
-
1.024
-
-
-
-
12 ns
- ns
27 MHz
13.5 MHz
Input Clock (CLKIN) low time
30 -
- ns
Input Clock (CLKIN) high time
30 -
- ns
Sample rate
Fs 4
- 50 kHz
RESET low time
(Note 11)
500 -
- ns
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.
When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.
See Internal Clock Generation section.
9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec
(CLKIN, XTAL1, XTAL2).
10. Sample rate specifications must not be exceeded.
11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage
reference to settle.
FSYNC in
TSIN
t s1 t h1 t s1 t h1
TSOUT
t pd2
t pd2
FSYNC out
SCLK
t pd1
t sckh
t sckw
t pd1
t sckl
t s1
t h1
SDIN
SDOUT
DS76F2
TS 1, Bit 7
t nz
t pd1
TS 1, Bit 7
TS 1, Bit 6
t pd1
TS 1, Bit 6
TS 8, Bit 0
TS 8, Bit 0
t hz
5
5 Page 
FSYNC
SCLK
CLKOUT
8.5 CLKOUT's
11 CLKOUT's
Data Mode -Read and Write
PIO Read
PIO Write
TSIN
SCLK
PIO Read
1 SCLK
Control Mode - Read Only
Notes:
1. DATA MODE READ - The data is sent out via SDOUT on the next frame.
2. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.
3. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.
They are independent of SCLK.
4. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.
Figure 5. PIO Pin Timing
CS4215
after power up. A calibration cycle will occur
immediately after leaving the reset state. A cali-
bration cycle will also occur immediately after
going from control mode to data mode (D/C go-
ing high). When powering up the CS4215, or
exiting the power down state, a minimum of
50 ms must occur, to allow the voltage reference
to settle, before initiating a calibration cycle.
This is achieved by holding RESET low or stay-
ing in control mode for 50 ms after power up or
exiting power down mode. The input offset error
will be calibrated for whichever input channel is
selected (microphone or line, using the IS bit).
Therefore, the IS bit should remain steady while
the codec is calibrating, although the other bits
input to the codec are ignored. Calibration takes
194 FSYNC cycles and SDOUT data bits will be
zero during this period. The A/D Invalid bit, ADI
(bit 7 in data time slot 6), will be high during
calibration and will go low when calibration is
finished.
Parallel Input/Output
Two pins are provided for parallel input/output.
These pins are open drain outputs and require
external pull-up resistors. Writing a zero turns on
the output transistor, pulling the pin to ground;
writing a one turns off the output transistor,
which allows an external resistor to pull the pin
high. When used as an input, a one must be writ-
ten to the pin, thereby allowing an external
device to pull it low or leave it high. These pins
can be read in control mode and their state is
recorded in Control Register 5. These pins can
be written to and read back in data mode using
Data Register 7. Figure 5 shows the Parallel In-
put/Output timing.
DS76F2
11
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