|
|
PDF EM63A165 Data sheet ( Hoja de datos )
| Número de pieza | EM63A165 | |
| Descripción | 16Mega x 16 Synchronous DRAM | |
| Fabricantes | Etron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EM63A165 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
EtronTech
EM63A165
16Mega x 16 Synchronous DRAM (SDRAM)
(Rev 1.1, Apr., 2007)
Features
• Fast access time from clock: 5/5.4 ns
• Fast clock rate: 166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 4M word x 16-bit x 4-bank
• Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Auto Refresh and Self Refresh
• 8192 refresh cycles/64ms
• CKE power down mode
• Single +3.3V power supply
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II Lead-free package
Overview
The EM63A165 SDRAM is a high-speed CMOS
synchronous DRAM containing 256 Mbits. It is internally
configured as 4 Banks of 2M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a Read
or Write command.
The EM63A165 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to maximize
its performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications.
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 DQMU
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Key Specifications
EM63A165
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
- 6/7
6/7 ns
5/5.4 ns
42/45 ns
60/63 ns
Ordering Information
Part Number
Frequency Package
EM63A165TS-6G
166MHz TSOP II
EM63A165TS-7G
143MHz TSOP II
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1 page  
EtronTech
EM63A165
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM BA0,1 A10 A0-9,12 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H
X X V Row address L L H H
BankPrecharge
Any H X X V L X L L H L
PrechargeAll
Any H X X X H X L L H L
Write
Write and AutoPrecharge
Active(3)
Active(3)
H
H
X X V L Column L H L
address
X X V H (A0 ~ A8) L H L
L
L
Read
Read and Autoprecharge
Active(3)
Active(3)
H
H
X X V L Column L H L H
address
X X V H (A0 ~ A8) L H L H
Mode Register Set
Idle H X X
OP code
LL L L
No-Operation
Any H X X X X X L H H H
Burst Stop
Active(4) H X X X X X L H H L
Device Deselect
Any H X X X X X H X X X
AutoRefresh
Idle H H X X X X L L L H
SelfRefresh Entry
Idle H L X X X X L L L H
SelfRefresh Exit
Idle H X X X
L H X XX X
(SelfRefresh)
LH H H
Clock Suspend Mode Entry
Active H L X X X X X X X X
Power Down Mode Entry
Any(5)
HX X X
H L X XX X
LH H H
Clock Suspend Mode Exit
Active L H X X X X X X X X
Power Down Mode Exit
Any L H X X X X H X X X
(PowerDown)
LH H H
Data Write/Output Enable
Active H X L X X X X X X X
Data Mask/Output Disable
Active H X H X X X X X X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
X
5 Rev 1.1 Apr. 2007
5 Page 
EtronTech
EM63A165
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6
CLK
DQM
tRP
COMMAND
WRITE
NOP
Precharge
NOP
NOP
Activate
NOP
ADDRESS
DQ
BANK
COL n
DIN
n
BANK (S)
tWR
DIN
n+1
ROW
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0 T 1
T2 T3
T4 T5
T6 T7
T8
CLK
COMMAND
Bank A
Activate
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
NOP
NOP
Write A
AutoPrecharge
NOP
DIN A0
DIN A1
DIN A0
DIN A1
NOP
tDAL
*
*
NOP
tDAL
NOP
NOP
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued at
the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the
mode register. One clock cycle is required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as all banks are in the idle state.
11 Rev 1.1 Apr. 2007
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM63A165.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EM63A165 | 16Mega x 16 Synchronous DRAM | Etron Technology |
| EM63A165TS | 16M x 16 bit Synchronous DRAM | Etron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |