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PDF PCA9517A Data sheet ( Hoja de datos )
| Número de pieza | PCA9517A | |
| Descripción | Level translating I2C-bus repeater | |
| Fabricantes | NXP Semiconductors | |
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PCA9517A
Level translating I2C-bus repeater
Rev. 4 — 9 May 2012
Product data sheet
1. General description
The PCA9517A is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus
applications. While retaining all the operating modes and features of the I2C-bus system
during the level shifts, it also permits extension of the I2C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of
400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus
for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus port A drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V
LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),
or PCA9518. Port A of two or more PCA9517As can be connected together, however, to
allow a star topography with port A on the common bus, and port A can be connected
directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can
be connected in series, port A to port B, with no build-up in offset voltage with only time of
flight delays to consider.
The PCA9517A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The EN pin can also be used to turn the drivers on and off under system control.
Caution should be observed to only change the state of the enable pin when the bus is
idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.3VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
Table 1. PCA9517 and PCA9517A comparison
Parameter
PCA9517[1]
electrostatic discharge, HBM
> 2 kV
PCA9517A[2]
> 5.5 kV
[1] PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system
updates.
[2] The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates
identically and should be used for all new designs and system updates.
1 page  
NXP Semiconductors
PCA9517A
Level translating I2C-bus repeater
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCC(B) and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I2C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I2C-bus devices in addition to SMBus devices. Standard mode I2C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus
system where Standard-mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
3.3 V
1.2 V
10 kΩ
SDA
SCL
BUS
MASTER
400 kHz
10 kΩ
VCC(B)
SDAB
SCLB
10 kΩ
VCC(A)
SDAA
SCLA
PCA9517A
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
bus B
bus A
002aad468
Fig 5. Typical application
The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
PCA9517A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 May 2012
© NXP B.V. 2012. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
PCA9517A
Level translating I2C-bus repeater
Table 5. Static characteristics …continued
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Enable
VIL
VIH
IIL(EN)
LOW-level input voltage
HIGH-level input voltage
LOW-level input current on
pin EN
VI = 0.2 V, EN; VCC = 3.6 V
−0.5 -
0.7VCC(B) -
- −10
ILI input leakage current
Ci input capacitance
VI = 3.0 V or 0 V
−1 -
-6
Max Unit
+0.3VCC(B) V
5.5 V
−30 μA
+1 μA
7 pF
[1] LOW-level supply voltage.
[2] VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAB/SCLB lines.
[3] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
10. Dynamic characteristics
Table 6. Dynamic characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.[1][2]
Symbol Parameter
Conditions
Min
tPLH
LOW to HIGH propagation delay
port B to port A; Figure 13
[4] 100
tPHL
HIGH to LOW propagation delay
port B to port A; Figure 11
VCC(A) ≤ 2.7 V
[5] 30
VCC(A) ≥ 3 V
10
tTLH LOW to HIGH output transition time port A; Figure 11
10
tTHL HIGH to LOW output transition time port A; Figure 11
VCC(A) ≤ 2.7 V
[5] 1
VCC(A) ≥ 3 V
tPLH
LOW to HIGH propagation delay
port A to port B; Figure 12
tPHL
HIGH to LOW propagation delay
port A to port B; Figure 12
20
[6] 25
[6] 60
tTLH LOW to HIGH output transition time port B; Figure 12
120
tTHL HIGH to LOW output transition time port B; Figure 12
30
tsu set-up time
EN HIGH before START condition [7] 100
th hold time
EN HIGH after STOP condition
[7] 100
Typ[3] Max
170 250
Unit
ns
80 110 ns
66 300 ns
20 30 ns
77 105 ns
70 175 ns
53 110 ns
79 230 ns
140 170 ns
48 90 ns
- - ns
- - ns
[1] Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on port B, and 167 Ω pull-up resistance and
57 pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the
propagation delay and transition times.
[2] Pull-up voltages are VCC(A) on port A and VCC(B) on port B.
[3] Typical values were measured with VCC(A) = 3.3 V at Tamb = 25 °C, unless otherwise noted.
[4] The tPLH delay data from port B to port A is measured at 0.5 V on port B to 0.5VCC(A) on port A when VCC(A) is less than 2 V, and 1.5 V
on port A if VCC(A) is greater than 2 V.
[5] Typical value measured with VCC(A) = 2.7 V at Tamb = 25 °C.
[6] The proportional delay data from port A to port B is measured at 0.3VCC(A) on port A to 1.5 V on port B.
[7] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
PCA9517A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 May 2012
© NXP B.V. 2012. All rights reserved.
11 of 22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PCA9517A.PDF ] | |
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