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PCA9517 데이터시트 PDF




Philips에서 제조한 전자 부품 PCA9517은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 PCA9517 기능
기능 Level translating I2C-bus repeater
제조업체 Philips
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PCA9517 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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PCA9517 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9517
Level translating I2C-bus repeater
Product data sheet
2004 Oct 05
Philips
Semiconductors




PCA9517 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Level translating I2C-bus repeater
Product data sheet
PCA9517
APPLICATION INFORMATION
A typical application is shown in Figure 3. In this example, the
system master is running on a 3.3 V I2C-bus while the slave is
connected to a 1.2 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
The PCA9517 is 5 V tolerant so it does not require any additional
circuitry to translate between 0.9 V to 5.5 V bus voltages and
2.7 V to 5.5 V bus voltages.
3.3 V
1.2 V
10 k
SDA
SCL
BUS
MASTER
400 kHz
10 k
VCCB
SDAB
10 k
VCCA
SDAA
SCLB SCLA
PCA9517
EN
10 k
SDA
SCL
SLAVE
400 kHz
BUS B
BUS A
SW02166
Figure 3. Typical application
VCCA
When the A side of the PCA9517 is pulled LOW by a driver on the
I2C-bus, a comparator detects the falling edge when it goes below
0.3VCCA and causes the internal driver on the B side to turn on,
causing the B side to pull down to about 0.5 V. When the B side of
the PCA9517 falls, first a CMOS hysteresis type input detects the
falling edge and causes the internal driver on the A side to turn on
and pull the A side pin down to ground. In order to illustrate what
would be seen in a typical application, refer to Figures 6 and 7. If the
bus master in Figure 3 were to write to the slave through the
PCA9517, waveforms shown in Figure 6 would be observed on the
A bus. This looks like a normal I2C transmission except that the
HIGH level may be as low as 0.9 V, and the turn on and turn off of
the acknowledge signals are slightly delayed.
On the B bus side of the PCA9517, the clock and data lines would
have a positive offset from ground equal to the VOL of the PCA9517.
After the 8th clock pulse, the data line will be pulled to the VOL of the
slave device which is very close to ground in this example. At the
end of the acknowledge, the level rises only to the LOW level set by
the driver in the PCA9517 for a short delay while the A bus side
rises above 0.3VCCA then it continues HIGH. It is important to note
that any arbitration or clock stretching events require that the LOW
level on the B bus side at the input of the PCA9517 (VIL) be at or
below 0.4 V to be recognized by the PCA9517 and then transmitted
to the A bus side.
VCCB
SDA
SCL
BUS
MASTER
10 k
10 k
10 k
SDAA SDAB
SCLA SCLB
PCA9517
EN
10 k
SDA
SCL
SLAVE
400 kHz
10 k
SDAA SDAB
SCLA SCLB
PCA9517
EN
10 k
SDA
SCL
SLAVE
400 kHz
10 k
10 k
SDAA SDAB
SDA
SCLA SCLB
PCA9517
EN
Figure 4. Typical star application
SCL
SLAVE
400 kHz
SW02347
Multiple PCA9517 A sides can be connected in a star configuration, allowing all nodes to communicate with each other.
2004 Oct 05
4

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PCA9517 전자부품, 판매, 대치품
Philips Semiconductors
Level translating I2C-bus repeater
Product data sheet
PCA9517
DC ELECTRICAL CHARACTERISTICS
VCC = 2.7 V to 3.3 V; GND = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
LIMITS
TYP.
MAX.
UNIT
Supplies
VCCB
VCCA
ICC
ICCH
ICCA
DC supply voltage
LOW-level DC supply voltage
Quiescent supply current for VCCA
Quiescent supply current,
both channels HIGH
Quiescent supply current,
both channels LOW
VCC = 3.6 V;
SDAn = SCLn = VCC
VCC = 3.6 V;
one SDA and one SCL = GND, other
SDA and SCL open
2.7
0.9
1.5
1.5
3.3 V
5.5 V
1 mA
5 mA
5 mA
ICCAc
Quiescent supply current in contention
VCC = 3.6 V;
SDAn = SCLn = GND
— 1.5
5 mA
Input and output SDAB and SCLB
VIH HIGH-level input voltage
VIL LOW-level input voltage (Note 1)
VILc LOW-level input voltage contention
(Note 1)
0.7VCCB
–0.5
–0.5
5.5
0.3VCCB
0.4
V
V
V
VIK
II
IIL
VOL
VOL–VILc
Input clamp voltage
Input leakage current
Input current LOW, SDA, SCL
LOW-level output voltage
LOW-level input voltage below
output low level voltage
II = –18 mA
VI = 3.6 V
VI = 0.2 V, SDA, SCL
IOL = 100 µA or 6 mA
Guaranteed by design
— — –1.2 V
——
±1 µA
——
10 µA
0.47 0.52
0.6
V
——
70 mV
IOH Output HIGH-level leakage current
CI/O Input/output capacitance
CI/O Input/output capacitance
Input and output SDAA and SCLA
VO = 3.6 V
VI = 3 V or 0 V; VCC = 3.3 V
VI = 3 V or 0 V; VCC = 0 V
——
—6
—6
10 µA
7 pF
7 pF
VIH
VIL
VIK
II
IIL
VOL
IOH
CI/O
CI/O
Enable
HIGH-level input voltage
LOW-level input voltage (Note 1)
Input clamp voltage
Input leakage current
Input current LOW, SDA, SCL
LOW-level output voltage
Output HIGH-level leakage current
Input/output capacitance
Input/output capacitance
II = –18 mA
VI = 3.6 V
VI = 0.2 V, SDA, SCL
IOL = 6 mA
VO = 3.6 V
VI = 3 V or 0 V; VCC = 3.3 V
VI = 3 V or 0 V; VCC = 0 V
0.7VCCA
–0.5
0.1
6
6
5.5
0.3VCCA
–1.2
±1
10
0.2
10
7
7
V
V
V
µA
µA
V
µA
pF
pF
VIL LOW-level input voltage
–0.5
— 0.3VCCB V
VIH HIGH-level input voltage
0.7VCCB
5.5
V
IIL Input current LOW, EN
VI = 0.2 V, EN; VCC = 3.6 V
— 10
30 µA
ILI Input leakage current
–1 —
1 µA
CI Input capacitance
VI = 3.0 V or 0 V
—6
7 pF
NOTE:
1. VIL specification is for the first LOW level seen by the SDAx/SCLx lines. VILc is for the second and subsequent LOW levels seen by the
SDAx/SCLx lines.
2004 Oct 05
7

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