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WM8912 데이터시트 PDF




Wolfson Microelectronics에서 제조한 전자 부품 WM8912은 전자 산업 및 응용 분야에서
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부품번호 WM8912 기능
기능 Ultra Low Power DAC
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WM8912 데이터시트, 핀배열, 회로
w
WM8912
Ultra Low Power DAC with Headphone Driver
for Portable Audio Applications
DESCRIPTION
The WM8912 is a high performance ultra-low power stereo
DAC optimised for portable audio applications.
The device features stereo ground-referenced headphone
amplifiers using the Wolfson ‘Class-W’ amplifier techniques -
incorporating an innovative dual-mode charge pump
architecture - to optimise efficiency and power consumption
during playback. The ground-referenced outputs eliminate
headphone coupling capacitors. The outputs include
common mode feedback paths to reject ground noise.
Control sequences for audio path setup can be pre-loaded
and executed by an integrated control write sequencer to
reduce software driver development and minimise pops and
clicks via Wolfson’s SilentSwitch™ technology.
A dynamic range controller provides compression and level
control to support a wide range of portable recording
applications. Anti-clip and quick release features offer good
performance in the presence of loud impulsive noises.
ReTuneTM Mobile 5-band parametric equaliser with fully
programmable coefficients is integrated for optimization of
speaker characteristics.
Common audio sampling frequencies are supported from a
wide range of external clocks, either directly or generated
using the integrated FLL.
The WM8912 can operate directly from a single 1.8V
switched supply. For optimal power consumption, the digital
core can be operated from a 1.0V supply.
FEATURES
3.8mW quiescent power consumption for DAC to
headphone playback
DAC SNR 96dB typical, THD -86dB typical
Class W ground-referenced headphone driver
- 28mW per channel into 30at <1% THD
- 32mW per channel into 15at <1% THD
Dynamic range controller
ReTune™ Mobile parametric equalizer
Integrated control write sequencer for pop minimised start-
up and shutdown
Single register write for default start-up and shutdown
sequences
On-chip FLL provides all necessary clocks
DAC supports standard sample rates from 8kHz to 96kHz
32-pin QFN package (4x4mm, 0.4mm pitch)
APPLICATIONS
Portable multimedia players
Multimedia handsets
Handheld gaming
WOLFSON MICROELECTRONICS plc
Production Data, February 2013, Rev 4.1
Copyright 2013 Wolfson Microelectronics plc




WM8912 pdf, 반도체, 판매, 대치품
WM8912
Production Data
DIGITAL-TO-ANALOGUE CONVERTER (DAC) ........................................................... 32 
DAC DIGITAL VOLUME CONTROL.............................................................................................................................. 32 
DAC SOFT MUTE AND SOFT UN-MUTE ..................................................................................................................... 34 
DAC MONO MIX............................................................................................................................................................ 35 
DAC DE-EMPHASIS...................................................................................................................................................... 35 
DAC SLOPING STOPBAND FILTER ............................................................................................................................ 36 
DAC OVERSAMPLING RATIO (OSR) .......................................................................................................................... 36 
OUTPUT SIGNAL PATH ............................................................................................... 37 
OUTPUT SIGNAL PATHS ENABLE.............................................................................................................................. 38 
HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE ........................................................................................... 38 
OUTPUT VOLUME CONTROL...................................................................................................................................... 41 
ANALOGUE OUTPUTS................................................................................................. 44 
HEADPHONE OUTPUTS – HPOUTL AND HPOUTR................................................................................................... 44 
LINE OUTPUTS – LINEOUTL AND LINEOUTR............................................................................................................ 44 
EXTERNAL COMPONENTS FOR GROUND REFERENCED OUTPUTS.................................................................... 45 
REFERENCE VOLTAGES AND MASTER BIAS........................................................... 46 
CHARGE PUMP ............................................................................................................ 46 
DC SERVO .................................................................................................................... 48 
DC SERVO ENABLE AND START-UP ......................................................................................................................... 48 
DC SERVO ACTIVE MODES ........................................................................................................................................ 51 
DC SERVO READBACK ............................................................................................................................................... 53 
DIGITAL AUDIO INTERFACE ....................................................................................... 53 
MASTER AND SLAVE MODE OPERATION................................................................................................................. 53 
OPERATION WITH TDM............................................................................................................................................... 54 
BCLK FREQUENCY ...................................................................................................................................................... 55 
AUDIO DATA FORMATS (NORMAL MODE) ................................................................................................................ 55 
AUDIO DATA FORMATS (TDM MODE)........................................................................................................................ 57 
DIGITAL AUDIO INTERFACE CONTROL..................................................................... 59 
AUDIO INTERFACE OUTPUT TRI-STATE ................................................................................................................... 59 
BCLK AND LRCLK CONTROL...................................................................................................................................... 60 
COMPANDING .............................................................................................................................................................. 61 
DIGITAL PULL-UP AND PULL-DOWN.......................................................................................................................... 63 
CLOCKING AND SAMPLE RATES ............................................................................... 64 
SYSCLK CONTROL ...................................................................................................................................................... 65 
CONTROL INTERFACE CLOCKING ............................................................................................................................ 66 
CLOCKING CONFIGURATION ..................................................................................................................................... 66 
DAC CLOCK CONTROL ............................................................................................................................................... 67 
OPCLK CONTROL ........................................................................................................................................................ 67 
TOCLK CONTROL ........................................................................................................................................................ 68 
DAC OPERATION AT 88.2K / 96K................................................................................................................................ 69 
FREQUENCY LOCKED LOOP (FLL) ............................................................................ 70 
FREE-RUNNING FLL CLOCK ....................................................................................................................................... 73 
EXAMPLE FLL CALCULATION..................................................................................................................................... 74 
GPIO OUTPUTS FROM FLL ......................................................................................................................................... 75 
EXAMPLE FLL SETTINGS............................................................................................................................................ 75 
GENERAL PURPOSE INPUT/OUTPUT (GPIO) ........................................................... 76 
IRQ/GPIO1..................................................................................................................................................................... 76 
BCLK/GPIO4.................................................................................................................................................................. 77 
INTERRUPTS................................................................................................................ 78 
CONTROL INTERFACE................................................................................................ 80 
CONTROL WRITE SEQUENCER ................................................................................. 83 
INITIATING A SEQUENCE............................................................................................................................................ 83 
PROGRAMMING A SEQUENCE .................................................................................................................................. 84 
DEFAULT SEQUENCES ............................................................................................................................................... 86 
w
PD, Rev 4.1, February 2013
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WM8912 전자부품, 판매, 대치품
Production Data
WM8912
PIN DESCRIPTION
NAME
QFN-32
TYPE
DESCRIPTION
IRQ/GPIO1
SCLK
1
Digital Input / Output
GPIO1 / Interrupt
2 Digital Input
Control interface clock input
SDA
DBVDD
3
Digital Input / Output
Control interface data input / output
4 Supply
Digital buffer supply (powers audio interface and control
interface)
DGND
DCVDD
5 Supply
6 Supply
Digital ground (return path for DCVDD and DBVDD)
Digital core supply
CPVDD
CPCA
CPGND
7 Supply
8 Analogue Input
9 Supply
Charge pump power supply
Charge pump flyback capacitor pin
Charge pump ground
CPCB
CPVOUTP
10 Analogue Input
11 Analogue Output
Charge pump flyback capacitor pin
Charge pump positive supply decoupling (powers
HPOUTL/R, LINEOUTL/R)
CPVOUTN
12 Analogue Output
Charge pump negative supply decoupling (powers
HPOUTL/R, LINEOUTL/R)
HPOUTL
13 Analogue Output
Left headphone output (line or headphone output)
HPOUTFB
HPOUTR
14 Analogue Output
15 Analogue Output
Headphone output ground loop noise rejection feedback
Right headphone output (line or headphone output)
LINEOUTL
LINEOUTFB
LINEOUTR
16 Analogue Output
17 Analogue Output
18 Analogue Output
Left line output 1 (line output)
Line output ground loop noise rejection feedback
Right line output 1 (line output)
DNC
DNC
19 n/a
20 n/a
Do Not Connect
Do Not Connect
VMIDC
AGND
21 Analogue Output
22 Supply
Midrail voltage decoupling capacitor
Analogue power return
AVDD
DNC
DNC
23 Supply
24 n/a
25 n/a
Analogue power supply
Do Not Connect
Do Not Connect
DNC
DNC
26 n/a
27 n/a
Do Not Connect
Do Not Connect
MCLK
BCLK/GPIO4
28 Digital Input
Master clock for DAC
29
Digital Input / Output
Audio interface bit clock / GPIO4
LRCLK
DNC
DACDAT
30
Digital Input / Output
Audio interface left / right clock
31 n/a
Do Not Connect
32 Digital Input
DAC digital audio data
GND_PADDLE
33
Die Paddle
Note:
It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
w
PD, Rev 4.1, February 2013
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