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WM8994 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 WM8994
기능 Multi-Channel Audio Hub CODEC
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WM8994 데이터시트, 핀배열, 회로
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WM8994
Multi-Channel Audio Hub CODEC for Smartphones
DESCRIPTION
FEATURES
The WM8994[1] is a highly integrated ultra-low power hi-fi
CODEC designed for smartphones and other portable devices
rich in multimedia features.
An integrated stereo class D/AB speaker driver and class W
headphone driver minimize power consumption during audio
playback.
The device requires only two voltage supplies, with all other
internal supply rails generated from integrated LDOs.
Stereo full duplex asynchronous sample rate conversion and
multi-channel digital mixing combined with powerful analogue
mixing allow the device to support a huge range of different
architectures and use cases.
A fully programmable parametric EQ provides speaker
compensation and a dynamic range controller can be used in
the ADC or DAC paths for maintaining a constant signal level,
maximizing loudness and protecting speakers against
overloading and clipping.
A smart digital microphone interface provides power regulation,
a low jitter clock output and decimation filters for up to four
digital microphones. A MIC activity detect with interrupt is
available.
Fully differential internal architecture and on-chip RF noise filters
ensure a very high degree of noise immunity. Active ground loop
noise rejection and DC offset correction help prevent pop noise
and suppress ground noise on the headphone outputs.
Hi-fi 24-bit 4-channel DAC and 2-channel ADC
100dB SNR during DAC playback (‘A’ weighted)
Smart MIC interface
- Power, clocking and data input for up to four digital MICs
- High performance analogue MIC interface
- MIC activity detect & interrupt allows processor to sleep
2W stereo (2 x 2W) class D/AB speaker driver
Capless Class W headphone drivers
- Integrated charge pump
- 5.3mW total power for DAC playback to headphones
4 Line outputs (single-ended or differential)
BTL Earpiece driver
Digital audio interfaces for multi-processor architecture
- Asynchronous stereo duplex sample rate conversion
- Powerful mixing and digital loopback functions
ReTuneTM Mobile 5-band, 6-channel parametric EQ
Programmable dynamic range controller
Dual FLL provides all necessary clocks
- Self-clocking modes allow processor to sleep
- All standard sample rates from 8kHz to 96kHz
Active noise reduction circuits
- DC offset correction removes pops and clicks
- Ground loop noise cancellation
Integrated LDO regulators
72-ball W-CSP package (4.511 x 4.023 x 0.7mm)
APPLICATIONS
Smartphones and music phones
Portable navigation
Tablets
eBooks
Portable Media Players
WOLFSON MICROELECTRONICS plc
Production Data, April 2012, Rev 4.4
[1] This product is protected by Patents US 7,622,984, US 7,626,445,US 7,765,019 and GB 2,432,765
Copyright 2012 Wolfson Microelectronics plc




WM8994 pdf, 반도체, 판매, 대치품
WM8994
Production Data
ANALOGUE OUTPUTS ............................................................................................... 137 
SPEAKER OUTPUT CONFIGURATIONS..................................................................................................................... 137 
HEADPHONE OUTPUT CONFIGURATIONS ............................................................................................................... 140 
EARPIECE DRIVER OUTPUT CONFIGURATIONS ..................................................................................................... 141 
LINE OUTPUT CONFIGURATIONS.............................................................................................................................. 141 
GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 145 
GPIO CONTROL ........................................................................................................................................................... 145 
GPIO FUNCTION SELECT ........................................................................................................................................... 148 
BUTTON DETECT (GPIO INPUT)................................................................................................................................. 149 
LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) .................................................................................................. 149 
SDOUT (4-WIRE SPI CONTROL INTERFACE DATA) ................................................................................................. 150 
INTERRUPT (IRQ) STATUS OUTPUT.......................................................................................................................... 150 
OVER-TEMPERATURE DETECTION........................................................................................................................... 150 
ACCESSORY DETECTION (MICBIAS CURRENT DETECTION) ................................................................................ 151 
FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT .................................................................................. 152 
SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT ................................................................................. 152 
DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION...................................................................... 152 
CONTROL WRITE SEQUENCER STATUS DETECTION ............................................................................................ 154 
DIGITAL CORE FIFO ERROR STATUS DETECTION.................................................................................................. 154 
OPCLK CLOCK OUTPUT.............................................................................................................................................. 155 
FLL CLOCK OUTPUT.................................................................................................................................................... 155 
INTERRUPTS .............................................................................................................. 156 
DIGITAL AUDIO INTERFACE...................................................................................... 162 
MASTER AND SLAVE MODE OPERATION................................................................................................................. 163 
OPERATION WITH TDM............................................................................................................................................... 163 
AUDIO DATA FORMATS (NORMAL MODE)................................................................................................................ 164 
AUDIO DATA FORMATS (TDM MODE) ....................................................................................................................... 167 
DIGITAL AUDIO INTERFACE CONTROL ................................................................... 169 
AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL................................................................................................ 169 
AIF1 - SIGNAL PATH ENABLE ..................................................................................................................................... 170 
AIF1 - BCLK AND LRCLK CONTROL ........................................................................................................................... 170 
AIF1 - DIGITAL AUDIO DATA CONTROL..................................................................................................................... 173 
AIF1 - MONO MODE ..................................................................................................................................................... 174 
AIF1 - COMPANDING ................................................................................................................................................... 175 
AIF1 - LOOPBACK ........................................................................................................................................................ 176 
AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL................................................................................................ 177 
AIF2 - SIGNAL PATH ENABLE ..................................................................................................................................... 178 
AIF2 - BCLK AND LRCLK CONTROL ........................................................................................................................... 178 
AIF2 - DIGITAL AUDIO DATA CONTROL..................................................................................................................... 181 
AIF2 - MONO MODE ..................................................................................................................................................... 182 
AIF2 - COMPANDING ................................................................................................................................................... 183 
AIF2 - LOOPBACK ........................................................................................................................................................ 183 
AUDIO INTERFACE AIF3 CONFIGURATION .............................................................................................................. 184 
DIGITAL PULL-UP AND PULL-DOWN.......................................................................................................................... 186 
CLOCKING AND SAMPLE RATES.............................................................................. 187 
AIF1CLK ENABLE ......................................................................................................................................................... 188 
AIF1 CLOCKING CONFIGURATION ............................................................................................................................ 189 
AIF2CLK ENABLE ......................................................................................................................................................... 191 
AIF2 CLOCKING CONFIGURATION ............................................................................................................................ 191 
MISCELLANEOUS CLOCK CONTROLS ...................................................................................................................... 193 
BCLK AND LRCLK CONTROL...................................................................................................................................... 196 
CONTROL INTERFACE CLOCKING ............................................................................................................................ 196 
FREQUENCY LOCKED LOOP (FLL) ............................................................................................................................ 197 
FREE-RUNNING FLL CLOCK....................................................................................................................................... 201 
GPIO OUTPUTS FROM FLL ......................................................................................................................................... 203 
EXAMPLE FLL CALCULATION..................................................................................................................................... 203 
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PD, April 2012, Rev 4.4
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WM8994 전자부품, 판매, 대치품
Production Data
PIN CONFIGURATION
WM8994
ORDERING INFORMATION
ORDER CODE TEMPERATURE RANGE
PACKAGE
WM8994ECS/R
Note:
Reel quantity = 3500
-40C to +85C
72-ball W-CSP
(Pb-free, Tape and reel)
MOISTURE
SENSITIVITY LEVEL
MSL1
PEAK SOLDERING
TEMPERATURE
260C
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PD, April 2012, Rev 4.4
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관련 데이터시트

부품번호상세설명 및 기능제조사
WM8991

Mobile Multimedia CODEC

Wolfson Microelectronics
Wolfson Microelectronics
WM8993

Audio Hub CODEC

Wolfson Microelectronics
Wolfson Microelectronics

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