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PDF CS42L56 Data sheet ( Hoja de datos )
| Número de pieza | CS42L56 | |
| Descripción | Stereo Codec | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS42L56
Ultralow Power, Stereo Codec with Class H Headphone Amp
DIGITAL to ANALOG FEATURES
5 mW Stereo Playback Power Consumption
99 dB Dynamic Range (A-wtd)
-86 dB THD+N
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-emphasis
– Master Volume Control (+12 to -102 dB in
0.5 dB steps)
– Soft-ramp & Zero-cross Transitions
– Programmable Peak-detect and Limiter
– Beep Generator with Full Tone Control
Stereo Headphone and Line Amplifiers
Step-down/Inverting Charge Pump
Class H Amplifier - Automatic Supply Adj.
– High Efficiency
– Low EMI
Pseudo-differential Ground-centered Outputs
High HP Power Output at -75 dB THD+N
– 2 x 20 mW Into 16 @ 1.8 V
1 VRMS Line Output @ 1.8 V
Analog Vol. Ctl. (+12 to -60 dB in 1 dB steps)
Analog In to Analog Out Passthrough
Pop and Click Suppression
ANALOG to DIGITAL FEATURES
3.5 mW Stereo Record Power Consumption
95 dB Dynamic Range (A-wtd)
-87 dB THD+N
Configurable Analog Inputs
– Two Pseudo-differential Stereo Inputs or
– One Pseudo-differential Stereo Inputs +
One Standard Stereo Input + One Standard
Mono Input or
– Three Standard Stereo Inputs
– Pseudo-differential Inputs Reduce
Common Mode Signal Noise
– 3:1 Stereo Input MUX for ADC or
Passthrough
Analog Programmable Gain Amplifier (PGA)
– +12 to -6 dB in 0.5 dB steps
– +10 dB or +20 dB Additional Gain for
Microphone Inputs
Programmable, Low-noise MIC Bias Output
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold &
Attack/Release Rates
Independent ADC Channel Control
High-pass Filter Disable for DC Measurements
Left Input 1
Pseudo Diff. Input /
Left Input 3
Right Input 1
Left Input 2
Pseudo Diff. Input /
Right Input 3
Right Input 2
Mic Bias Output
Analog Supply (VA)
+1.62 V to +2.75 V
Digital Supply (VLDO)
+1.62 V to +2.75 V
Charge Pump Supply (VCP)
+1.62 V to +2.75 V
LDO Regulator
Step-Down
Inverting
+VHP -VHP
0, +10, or
+20 dB
-6 to +12 dB
0.5 dB Steps
Multi-bit
ADC
ALC Beep
Attenuator,
Boost, Mix
Mono mix,
Limiter, Bass,
Treble Adjust
Multi-bit
DAC
ALC HPF
Programmable Mic Bias
Control Port Serial Audio Port
Level Shifter
-
+
+
-
-
+
+
-
Left Headphone Output
Pseudo Diff. Input
Right Headphone Output
Left Line Output
Pseudo Diff. Input
Right Line Output
http://www.cirrus.com
+1.62 V to +3.63 V
Interface Supply
I²C or SPI
Control
I²S or Left Justified
Serial Audio Input/
Output
Copyright Cirrus Logic, Inc. 2014
(All Rights Reserved)
Ground-Centered
Amplifiers
FEB '14
DS851F2
1 page  
CS42L56
6.11.2 HP/Line De-Emphasis ......................................................................................................... 65
6.11.3 Playback Channels B=A ...................................................................................................... 65
6.11.4 Invert PCM Signal Polarity .................................................................................................. 65
6.12 DSP Mute Controls (Address 0Ch) ............................................................................................... 66
6.12.1 ADC Mixer Channel x Mute ................................................................................................. 66
6.12.2 PCM Mixer Channel x Mute ................................................................................................ 66
6.12.3 Master Playback Mute ......................................................................................................... 66
6.13 ADCx Mixer Volume: ADCA (Address 0Dh) & ADCB (Address 0Eh) ........................................... 66
6.13.1 ADC Mixer Channel x Volume ............................................................................................. 66
6.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h) .......................................... 67
6.14.1 PCM Mixer Channel x Volume ............................................................................................ 67
6.15 Analog Input Advisory Volume (Address 11h) .............................................................................. 68
6.15.1 Analog Input Advisory Volume ............................................................................................ 68
6.16 Digital Input Advisory Volume (Address 12h) ............................................................................... 68
6.16.1 Digital Input Advisory Volume ............................................................................................. 68
6.17 Master Volume Control:
MSTA (Address 13h) & MSTB (Address 14h) ...................................................................................... 69
6.17.1 Master Volume Control ........................................................................................................ 69
6.18 Beep Frequency & On Time (Address 15h) ................................................................................. 69
6.18.1 Beep Frequency .................................................................................................................. 69
6.18.2 Beep On Time ..................................................................................................................... 70
6.19 Beep Volume & Off Time (Address 16h) ...................................................................................... 70
6.19.1 Beep Off Time ..................................................................................................................... 70
6.19.2 Beep Volume ....................................................................................................................... 71
6.20 Beep & Tone Configuration (Address 17h) ................................................................................... 71
6.20.1 Beep Configuration .............................................................................................................. 71
6.20.2 Treble Corner Frequency .................................................................................................... 71
6.20.3 Bass Corner Frequency ...................................................................................................... 72
6.20.4 Tone Control Enable ........................................................................................................... 72
6.21 Tone Control (Address 18h) ......................................................................................................... 72
6.21.1 Treble Gain .......................................................................................................................... 72
6.21.2 Bass Gain ............................................................................................................................ 72
6.22 ADC & PCM Channel Mixer (Address 19h) .................................................................................. 73
6.22.1 PCM Mix Channel Swap ..................................................................................................... 73
6.22.2 ADC Mix Channel Swap ...................................................................................................... 73
6.23 AIN Reference Configuration, ADC MUX (Address 1Ah) ............................................................. 73
6.23.1 Analog Input 2 x Reference Configuration .......................................................................... 73
6.23.2 Analog Input 1 x Reference Configuration .......................................................................... 73
6.23.3 ADC x Input Select .............................................................................................................. 74
6.24 HPF Control (Address 1Bh) .......................................................................................................... 74
6.24.1 ADCx High-Pass Filter ........................................................................................................ 74
6.24.2 ADCx High-Pass Filter Freeze ............................................................................................ 74
6.24.3 HPF x Corner Frequency .................................................................................................... 74
6.25 Misc. ADC Control (Address 1Ch) ................................................................................................ 75
6.25.1 ADC Channel B=A .............................................................................................................. 75
6.25.2 PGA Channel B=A .............................................................................................................. 75
6.25.3 Digital Sum .......................................................................................................................... 75
6.25.4 Invert ADC Signal Polarity ................................................................................................... 75
6.25.5 ADC Mute ............................................................................................................................ 75
6.26 Gain & Bias Control (Address 1Dh) .............................................................................................. 76
6.26.1 PGA x Preamplifier Gain ..................................................................................................... 76
6.26.2 Boostx ................................................................................................................................. 76
6.26.3 Microphone Bias Output Level ............................................................................................ 76
6.27 PGA x MUX, Volume: PGA A (Address 1Eh) & PGA B (Address 1Fh) ........................................ 76
DS851F2
5
5 Page 
2. TYPICAL CONNECTION DIAGRAMS
CS42L56
1 µF **
** 0.1 µF ** 0.1 µF
+1.65 V to +2.75 V
Note 1
2.2 µF **
+1.65 V to +2.75 V
Note 1
2.2 µF **
Note 2
2.2 µF **
2.2 µF **
Note 1
2.2 µF **
Digital Audio
Processor
VDFILT VLDO
VA
47 k
+VHPFILT
VCP
HPREF
HPOUTB
0.1 µF
** 33
HPOUTA
HPDETECT
** 33
0.1 µF
Headphone Out
Left & Right
CS42L56
FLYP
FLYC
FLYN
-VHPFILT
MCLK
SCLK
LRCK
SDIN
SDOUT
RESET
SCL\CCLK
SDA\CDIN
AD0\CS
LINEOUTA
LINEREF
LINEOUTB
562
3300 pF
* LPF is Optional
562
*3300 pF
Rext Line Level Out
Rext Left & Right
AIN1A
AIN1REF
AIN1B
Note 4
1 µF
1800 pF *
** *
1800 pF
**
1 µF 100
** 100
1 µF
100 k
100 k
Analog
Input 1
AIN2A
AIN2REF
AIN2B
1 µF 1800 pF *
**
1 µF 100
100 k
** *
1800 pF
** 100
1 µF
100 k
Analog
Input 2
Rp Rp
+1.65 V to +3.63 V
** 0.1 µF
VL
AGND
TSTN
TSTN
AFILTA
AFILTB
VQ
FILT+
GND/Thermal Pad
Note 3
**
1000 pF 1000 pF
**
2.2 µF
**
2.2 µF
* NPO /C0G dielectric capacitors.
** Low ESR, X7R/X5R dielectric capacitors.
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manufacturer’s data sheet, capaciotof rtyspischaloXu7lRd/Xb5eRsceelreamctiec dcabpaacsiteodrs odnevtiahteesmfrionmimthuemnoomuintapluvtalpuoe wbyear apenrcdenmtaagxeimspuecmifieddisintothrteiomnanreufqacutiurreedr’s. data
2. The headphone amplifier’s outpsuhtepeto, wcaepracaitnodrs dsihsotuoldrtbioensealerecterdatbeadseudsoinngthethmeinnimomuminoaultpcuat ppoawceitraanncdemsahxiomwumn adinstdorutiosninrgeqtuhireed.default charge pump switching frequency.
The
may
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from the nominal value by a percetnhteacgaepascpiteanccifeiemdusint itnhcereamsea. nSuinfcaectthuereacrt’usadl vaatlauesohfetyepti,ccalaXp7aRc/Xit5oRrscesrhamouicldcabpeacsitoerlsedcetevidatebsafsroemd tohne nthomeinmailnviamluuem output power, maximum
distortion and maximum charge pubymappsewrceitncthaginegspfereciqfieudeinnctyhermeqanuuirfaecdtu. rer’s data sheet, capacitors should be selected based on the minimum output
3. Additional bulk capacitance maypobweera, mddaxeimdutmo idmistporrotiovneaPndSmRaRximautmlocwhafrrgeeqpuuemnpcsiewsit.ching frequency required.
4. These capacitors serve
are only needed when the
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panladcsehdoualdsbce lpolasceedasaspossible
is bypassed.
to
the
inputs.
They
Figure 1. Typical Connection Diagram - Four Pseudo-Differential Analog Inputs
DS851F2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS42L56.PDF ] | |
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