PDF WM0011 Data sheet ( Hoja de datos )

Número de pieza	WM0011
Descripción	General Purpose Low-Power Audio DSP
Fabricantes	Wolfson Microelectronics
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No Preview Available ! w WM0011 General Purpose Low-Power Audio DSP DESCRIPTION WM0011 Audio DSP provides Wolfson HD audio quality, with a power-budget targeted at handheld battery-powered audio devices. WM0011 combines the advanced Tensilica HiFi EP™ audio DSP with an I/O and peripheral set optimized for flexible integration into smartphones, tablets and other portable consumer electronics devices. WM0011 is ideal for extremely power-efficient implementations of advanced voice enhancement, telephony noise reduction, voice and music CODECs and general audio enhancement. A very wide range of audio CODECs, voice CODECs and third-party algorithms from such companies as Waves Audio, SRS Labs and Dolby are available, providing a rich portfolio of audio-processing options that can be integrated into a device with no additional software development. WM0011 comes in a space-saving 3x3mm 49-ball W-CSP package with 0.4mm pitch. APPLICATIONS  Wireless audio devices – headsets, microphones, speakerphones  Portable media devices  Automotive  General purpose digital signal processor for consumer audio applications  Smartphones FEATURES  260MHz Tensilica HiFi EP™ 24-bit audio digital signal processor - C-programmable with advanced debugging and profiling tool set - 256kB local RAM memory - 36kB Instruction / Data cache memory - 384kB general-purpose system RAM - Flexible boot options with 32kB boot ROM - 32 Channel DMA - XTAL or CMOS clock input - Low-power programmable PLL  Security - Support for HW Authentication - Random Number Generator (RNG) to assist security algorithms  Peripherals - SPI Master / Slave interface - 3 x multi-channel AIF interfaces, including I2S and TDM - UART - I2C Master - I2C Slave - 3 x 32-bit general-purpose timer modules - Watchdog timer - On-chip JTAG debug unit and trace buffer - GPIO  Software-defined standby modes for extended battery life WOLFSON MICROELECTRONICS plc Production Data, August 2013, Rev 4.1 Copyright 2013 Wolfson Microelectronics plc 1 page WM0011 Production Data CCM_IOCTRL7 – I/O CONTROL 7 REGISTER ....................................................................................................83 CCM_IOCTRL8 – I/O CONTROL 8 REGISTER ....................................................................................................84 CCM_IOCTRL9 – I/O CONTROL 9 REGISTER ....................................................................................................86 CCM_IOCTRL10 – I/O CONTROL 10 REGISTER ................................................................................................86 CCM_IOCTRL11 – I/O CONTROL 11 REGISTER ................................................................................................88 TIMER (TMR) MODULES ........................................................................................................89 TIMER DESCRIPTION ..........................................................................................................................................89 TIMER INTERRUPTS............................................................................................................................................90 TIMER REGISTER MAP........................................................................................................................................90 TMR_PRESCALE – TIMER PRESCALE REGISTER............................................................................................90 TMR_MAX_CNT – TIMER MAXIMUM COUNT REGISTER..................................................................................91 TMR_CUR_CNT – TIMER CURRENT COUNT REGISTER .................................................................................91 TMR_CTRL – TIMER CONTROL REGISTER.......................................................................................................92 TMR_INT_STATUS – TIMER INTERRUPT STATUS REGISTER ........................................................................93 I2C INTERFACE MODULE.......................................................................................................94 I2C FEATURES .....................................................................................................................................................94 I2C TRANSFERS ..................................................................................................................................................94 I2C INTERRUPTS .................................................................................................................................................97 I2C REGISTER MAP .............................................................................................................................................98 I2C_CFG – I2C CONFIGURATION REGISTER.....................................................................................................99 I2C_STATUS – I2C STATUS REGISTER ...........................................................................................................100 I2C_INT_CTRL – I2C INTERRUPT CONTROL REGISTER ................................................................................102 I2C_MCTRL – I2C MASTER ACCESS CONTROL REGISTER...........................................................................102 I2C_MRXDATA – I2C MASTER RECEIVE DATA REGISTER ............................................................................104 I2C_MTXDATA – I2C MASTER TRANSMIT DATA REGISTER ..........................................................................104 I2C_BAUD – I2C BAUD RATE REGISTER..........................................................................................................106 I2C_SRXDATA – I2C SLAVE RECEIVE DATA REGISTER ................................................................................107 I2C_STXDATA – I2C SLAVE TRANSMIT DATA REGISTER ..............................................................................108 I2C_SLV_ADDR – I2C SLAVE ADDRESS REGISTER .......................................................................................109 FUSE MEMORY.....................................................................................................................110 FUSE MEMORY DEFINITION.............................................................................................................................110 CYCLIC REDUNDANCY CHECK (CRC).............................................................................................................111 SOFTWARE AUTHENTICATION ........................................................................................................................112 GENERAL PURPOSE INPUT/OUTPUT (GPIO) MODULE ...................................................113 GPIO FEATURES................................................................................................................................................113 INPUT / OUTPUT CONTROL..............................................................................................................................113 LEVEL/EDGE INTERRUPT CONTROL...............................................................................................................113 GPIO INTERRUPTS ............................................................................................................................................114 GPIO REGISTER MAP........................................................................................................................................115 GPIO_OUT – GPIO OUTPUT REGISTER ..........................................................................................................115 GPIO_IN – GPIO INPUT REGISTER ..................................................................................................................116 GPIO_DIR – GPIO DIRECTION REGISTER.......................................................................................................117 GPIO_INV – GPIO INVERSION REGISTER .......................................................................................................117 EDGE DETECTION .............................................................................................................................................118 GPIO_EDGE0 – GPIO EDGE DETECTION 0 REGISTER..................................................................................119 GPIO_EDGE1 – GPIO EDGE DETECTION 1 REGISTER..................................................................................119 GPIO_INT_CTRL – GPIO INTERRUPT CONTROL REGISTER.........................................................................120 GPIO_INT_CLR – GPIO INTERRUPT CLEAR REGISTER ................................................................................121 GPIO_INT_MSK – GPIO INTERRUPT MASK REGISTER..................................................................................122 GPIO_INT_VECT – GPIO INTERRUPT VECTOR REGISTER ...........................................................................123 GPIO_INT_STS – GPIO INTERRUPT STATUS REGISTER ..............................................................................124 INTERRUPT CONTROLLER (IRQC) MODULE.....................................................................125 INTERRUPT CONTROLLER (IRQC) FEATURES...............................................................................................125 INPUT / OUTPUT CONTROL..............................................................................................................................125 w PD, Rev 4.1, August 2013 5 5 Page WM0011 Production Data PIN NAME NO B7 AIF3BCLK/SPISCLK UART / I2C Master & Slave Interfaces F3 UARTRX/SDA1/SDA2/GPIO22 G3 UARTTX/SCLK1/SCLK2/GPIO23 GPIO F1 F2 D3 E2 D2 E1 B3 C2 C3 A3 B2 Debug C4 A6 C7 C6 C5 A7 D5 Other B1 D1 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 TCK TDEBUG/TMSDEBUG TDI TDO TMSDFT ¯T¯O¯C¯D¯¯R¯S¯T¯ ¯T¯R¯S¯T¯ DNC NC TYPE Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input Input / Output Input Output Input Input Input PULL DEVICE Pull-Down DESCRIPTION AIF3 bit clock / SPI serial clock1 Pull-Down Pull-Down UART RX / Serial data 1 (slave) / Serial data 2 (master) / GPIO2 UART TX / Serial clock 1 (slave) / Serial clock 2 (master) / GPIO2 Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down Pull-Up/Down GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin GPIO pin Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down JTAG clock Test Mode Debug output / Test Mode Select input JTAG data input JTAG data output JTAG mode select input Maskable chip reset from the debug tool JTAG Test Access Port (TAP) block reset Do Not Connect Not used - connect to GND. Notes: 1. The SPI interface I/O pads are multiplexed with AIF3 2. The UART, I2C master and I2C slave signals are multiplexed into two I/O pads. 3. The I/O pad multiplexers are configured during the boot-up sequence, as determined by the Custom Fuse settings. Table 1 identifies the default power-up condition of each of the input / output pins, assuming that the Custom Fuses are not programmed. Application-specific parameters for configuring the input / output pins, and many other parameters, may be selected using the integrated one-time-programmable fuses. See “Boot Sequence Control” for further details. PIN NAME NO E7 XTI E6 XTO A5 R¯¯E¯S¯E¯T¯ E5 ¯S¯T¯A¯N¯¯D¯B¯Y¯ E3 I¯R¯Q¯ G4 CLKOUT/GPIO28 G6 AIF1TXDAT F6 AIF1RXDAT w DEFAULT FUNCTION / RESET CONDITION (FUSES NOT PROGRAMMED) XTI input XTO output R¯¯E¯S¯E¯T¯ input Pull-up enabled ¯S¯T¯A¯N¯¯D¯B¯Y¯ input Pull-up enabled I¯R¯Q¯ output Pull-up enabled CLKOUT output Pull-down enabled AIF1TXDAT output Pull-down enabled AIF1RXDAT input Pull-down enabled PD, Rev 4.1, August 2013 11 11 Page

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Número de pieza	Descripción	Fabricantes
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