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PDF AT25SF161 Data sheet ( Hoja de datos )
| Número de pieza | AT25SF161 | |
| Descripción | SPI Serial Flash Memory | |
| Fabricantes | Adesto | |
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AT25SF161
16-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
Die in Wafer Form
Hi-Rel Plastic Available
8-ball die Ball Grid Array (dBGA - WLCSP)
DS-25SF161–046F–4/2016
1 page  
2. Block Diagram
Figure 2-1. Block Diagram
Control and
CS Protection Logic
SCK
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
Y-Decoder
WP (I/O2)
HOLD (I/O3)
X-Decoder
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF161 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
AT25SF161
DS-25SF161–046F–4/2016
5
5 Page 
Figure 6-3. Dual-Output Read Array
CCSS
SCK
SCK
6, 6,2
I/OS0 O
(SI)
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
23&2'(
$''5(66%,76$$
DON'T &$5(
OUTPUT
OUTPUT
DAT$%<7( DAT$%<7(
0 0 1Ad1dre1ss 0Bits1 1 A A A AAddrAessABits A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4
MSB A23-A16 MSAB15-A8
A7-A0
MSBM7-M0
Byte 1
Byte 2
HIGH-IMAP22EDAA20NCAE18 A16 A14 A
MSB
A0 M6 M4 M2 M0 D6 D4 D2 D0 D6
D7 D5 D3 D1 D7 D5 D3 D1 D7 D5
MSB
MSB
MSB
I/O1
(SO)
A23 A21 A19 A17 A15 A
MSB
A1 M7 M5 M3 M1 D7 D5 D3 D1 D7
6.3 Dual-I/O Read Array (BBh)
The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address
with two bits of address on each clock and two bits of data on every clock cycle.
The Dual-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To
perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location
of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be
clocked into the device.
After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M41,0)
6.3.1
Dual-I/O Read Array (BBh) with Continuous Read Mode
The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read Mode
bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-5. The upper nibble of the (M7-4) controls the
length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The
lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O
command (after CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This
reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is
asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and
AT25SF161
DS-25SF161–046F–4/2016
11
11 Page | ||
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