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74HC40105 데이터시트 PDF




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부품번호 74HC40105 기능
기능 4-bit x 16-word FIFO register
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74HC40105 데이터시트, 핀배열, 회로
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 4 — 29 January 2016
Product data sheet
1. General description
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Input levels:
For 74HC40105: CMOS level
For 74HCT40105: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C




74HC40105 pdf, 반도체, 판매, 대치품
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
5. Pinning information
5.1 Pinning
+&
+&7
2( 
',5 
6, 
' 
' 
' 
' 
*1' 
 9&&
 62
 '25
 4
 4
 4
 4
 05
DDD
Fig 5. Pin configuration SO16
+&
+&7
2( 
',5 
6, 
' 
' 
' 
' 
*1' 
 9&&
 62
 '25
 4
 4
 4
 4
 05
DDD
Fig 6. Pin configuration (T)SSOP16
5.2 Pin description
Table 2. Pin description
Symbol
Pin
OE 1
DIR 2
SI 3
D0 to D3
4, 5, 6, 7
GND
8
MR 9
Q0 to Q3
13, 12, 11, 10
DOR
14
SO 15
VCC 16
Description
output enable input (active LOW)
data-in-ready output
shift-in input (LOW-to-HIGH, edge triggered)
parallel data input
ground (0 V)
asynchronous master-reset input (active HIGH)
data output
data-out-ready output
shift-out input (HIGH-to-LOW, edge triggered)
supply voltage
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 36

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74HC40105 전자부품, 판매, 대치품
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6.6 Expanded format
With the addition of a logic gate, the FIFO is easily expanded to increase word length (see
Figure 19). The basic operation and timing are identical to a single FIFO, except for an
additional gate delay on the flag outputs. If during application, the following occurs:
SI is held HIGH when the FIFO is empty, some additional logic is required to produce
a composite DIR pulse (see Figure 9 and Figure 20).
Due to the part-to-part spread of the ripple through time, the SI signals of FIFOA and
FIFOB do not always coincide. As a result, the AND-gate does not produce a composite
flag signal. The solution is given in Figure 20. The “40105” is easily cascaded to increase
the word capacity and no external components are needed. In the cascaded
configuration, the FIFOs perform all necessary communications and timing. The minimum
flag pulse widths and the flag delays determine the intercommunication speed. The data
rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and
beyond 32-words x 4-bits (see Figure 21).
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V
IO output current
VO = 0.5 V to (VCC + 0.5 V)
0.5
[1] -
[1] -
-
+7 V
20 mA
20 mA
25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
SO16 package
(T)SSOP16 package
-
50
65
[2] -
[3] -
+50
-
+150
500
500
mA
mA
C
mW
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
[3] For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 36

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