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PDF PT7C4311 Data sheet ( Hoja de datos )
| Número de pieza | PT7C4311 | |
| Descripción | Real-time Clock Module | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PT7C4311
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Real-time Clock Module (I2C Bus)
Features
Description
Support I2C-Bus (High speed mode 400kHz)
The PT7C4311 serial real-time clock is a low-power
Includes time (Hour/Minute/Second) and calendar
clock/calendar with a programmable square-wave output.
(Century/Year/Month/Date/Day) counter functions
Address and data are transferred serially via a 2-wire
Year 2000 compliant
Automatic switch-over and deselect circuitry
Time keeping voltage: 1.2V to 5.5V
Software clock calibration
56 bytes of general purpose RAM
Ultra-low battery supply current of 0.3A
Low operating current of 70A
Battery or super cap back-up
Operating temperature: -40°C to 85°C
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in the 24-
hour format indicator.
Table 1 shows the basic functions of PT7C4311. More
details are shown in section: overview of functions.
Pin Configuration
Automatic leap year compensation
Special software programmable output
Pin Description
Pin no.
Pin Type
Description
1 X1 I Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected between them. Or
external clock input.
2 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
3
VBAT
P Battery Supply Voltage. When VCC>VSO1, VCC will power the IC. While VCC<VSO1, VBAT
will power the IC.
4
GND
P Ground.
5
SDA
I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open-drain output and requires an external pull-up resistor.
6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface.
Frequency Test / Output Driver. Open drain. 512Hz output when Frequency Test is selected.
7 FT/OUT O
Output DC level by register selection. Frequency Test is prior.
8
VCC
P Supply Voltage. When VCC>VSO1, VCC will power the IC. While VCC<VSO1, VBAT will power
the IC.
Note: 1. VSO: Battery Back-up Switchover Voltage
2015-06-0002
PT0322-8
06/16/15
1
1 page  
PT7C4311
Real-time Clock Module (I2C Bus)
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AC Electrical Characteristics
Sym Description
VHM Rising and falling threshold voltage high
VHL Rising and falling threshold voltage low
Value
0.8 VCC
0.2 VCC
Unit
V
V
Signal
tf
Over the operating range
Symbol
Item
fSCL
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tBUF
tLOW
tHIGH
tr
tf
CB
SCL clock frequency
START condition set-up time
START condition hold time
Data set-up time (RTC read/write)
Data hold time (RTC read/write)
STOP condition setup time
Bus idle time between a START and STOP condition
When SCL = "L"
When SCL = "H"
Rise time for SCL and SDA
Fall time for SCL and SDA
Capacitance load for each bus line
tr
STAND Mode (I2C)
Min.
Max.
- 100
4.7 -
4.0 -
250 -
0-
4.0 -
4.7 -
4.7 -
4.0 -
- 1.0
- 0.3
0 400
VHM
VLM
FAST Mode (I2C)
Min.
Max.
- 400
0.6 -
0.6 -
100 -
0 0.9
0.6 -
1.3 -
1.3 -
0.6 -
20+0.1CB
20+0.1CB
0
0.3
0.3
400
Unit
kHz
s
s
ns
us
s
s
s
s
s
s
pF
Timing Diagram
S
SCL
SDA
tHD;STA
tLOW
fSCL
tSU;DAT
tHIGH
tHD;DAT
Sr
tHD;STA
tSU;STA
P tSU;STA
tSP
tBUF
tSU;STO
tHD;STA
S Start condition
Sr Restart condition
P Stop condition
2015-06-0002
PT0322-8
06/16/15
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PT7C4311
Real-time Clock Module (I2C Bus)
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c) Starting and Stopping I2C Bus Communications
Fig.2 Starting and stopping on I2C bus
START condition, repeated START condition, and STOP condition
START condition
SDA level changes from high to low while SCL is at high level
STOP condition
SDA level changes from low to high while SCL is at high level
Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
d) Data Transfers and Acknowledge Responses during I2C-BUS Communication
Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note: with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
2015-06-0002
PT0322-8
06/16/15
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet PT7C4311.PDF ] | |
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