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PDF 74LV14 Data sheet ( Hoja de datos )
| Número de pieza | 74LV14 | |
| Descripción | Hex inverting Schmitt trigger | |
| Fabricantes | NXP Semiconductors | |
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74LV14
Hex inverting Schmitt trigger
Rev. 6 — 12 December 2011
Product data sheet
1. General description
The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC14 and 74HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
1 page  
NXP Semiconductors
74LV14
Hex inverting Schmitt trigger
10. Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
VOH
VOL
II
ICC
ICC
CI
HIGH-level output voltage
LOW-level output voltage
input leakage current
supply current
additional supply current
input capacitance
VI = VT+ or VT
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
VI = VT+ or VT
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
VI = VCC or GND;
VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V
Min Typ[1] Max
- 1.2
1.8 2.0
2.5 2.7
2.8 3.0
4.3 4.5
2.4 2.82
3.6 4.2
-
-
-
-
-
-
-
-0 -
- 0 0.2
- 0 0.2
- 0 0.2
- 0 0.2
- 0.25 0.40
- 0.35 0.55
- - 1.0
- - 20.0
- - 500
- 3.5 -
Tamb = 40 C
to +125 C
Min Max
Unit
- -V
1.8 - V
2.5 - V
2.8 - V
4.3 - V
2.2 - V
3.5 - V
- -V
- 0.2 V
- 0.2 V
- 0.2 V
- 0.2 V
- 0.50 V
- 0.65 V
- 1.0 A
- 40 A
- 850 A
- - pF
[1] Typical values are measured at Tamb = 25 C.
74LV14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
16. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
74LV14
Hex inverting Schmitt trigger
SOT27-1
D
L
Z
14
e
pin 1 index
b
A2 A
A1
wM
b1
8
ME
c
(e 1)
MH
E
17
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36 19.50 6.48
0.23 18.55 6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.02
0.13
0.068 0.021 0.014
0.044 0.015 0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01 0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
SOT27-1
IEC
050G04
REFERENCES
JEDEC
JEITA
MO-001
SC-501-14
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 15. Package outline SOT27-1 (DIP14)
74LV14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
11 of 19
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 74LV14.PDF ] | |
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