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IDT7130LA 데이터시트 PDF




Integrated Device Technology에서 제조한 전자 부품 IDT7130LA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 IDT7130LA 자료 제공

부품번호 IDT7130LA 기능
기능 HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
제조업체 Integrated Device Technology
로고 Integrated Device Technology 로고


IDT7130LA 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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IDT7130LA 데이터시트, 핀배열, 회로
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
IDT7130SA/LA
IDT7140SA/LA
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT7130/IDT7140LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A9L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/WL
10
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
10
CER
OER
R/WR
INTL(2)
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
©2016 Integrated Device Technology, Inc.
1
,
I/O0R-I/O7R
BUSYR(1,2)
A9R
A0R
INTR(2)
2689 drw 01
MAY 2016
DSC-2689/16




IDT7130LA pdf, 반도체, 판매, 대치품
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
20 19 18 17 16 15 14 13 12 11 10 9 8
21 7
22 6
23 5
24 4
25 3
26 7130/40
2
27
J52(4)
1
28 52
29 51
30 50
31 49
32 48
33 47
34 35 36 37 38 39 40 41 42 43 44 45 46
A0L
OEL
N/C
INTL
BUSYL
R/WL
CEL
VCC
CER
R/WR
BUSYR
INTR
N/C
2689 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
4

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IDT7130LA 전자부품, 판매, 대치품
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%)
7130X20(2)
7140X20(2)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
Version
Typ. Max. Typ. Max.
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL,
Outputs Disabled
f = fMAX(3)
COM'L SA 110 250 110 220
LA 110 200 110 170
MIL &
IND
SA ____
LA ____
____ 110 280
____ 110 220
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
COM'L
SA 30
65
30
65
LA 30 45 30 45
MIL & SA ____ ____ 30 80
IND LA ____ ____ 30 60
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(6)
Active Port OutputsDisabled,
f=fMAX(3)
COM'L SA 65 165 65 150
LA 65 125 65 115
MIL & SA ____ ____ 65 160
IND LA ____ ____ 65 125
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM'L
SA 1.0
15
1.0
15
LA 0.2 5 0.2 5
MIL &
IND
SA ____
LA ____
____ 1.0 30
____ 0.2 10
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L SA 60 155 60 145
LA 60 115 60 105
MIL & SA ____ ____ 60 155
IND LA ____ ____ 60 115
7130X35
7140X35
Com'l
& Military
Typ. Max.
110 165
110 120
110 230
110 170
25 65
25 45
25 80
25 60
50 125
50 90
50 150
50 115
1.0 30
0.2 10
____ ____
____ ____
45 110
45 85
45 145
45 105
Unit
mA
mA
mA
mA
mA
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL,
Outputs Disabled
f = fMAX(3)
Test Condition
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled,
f=fMAX(3)
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(6)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
Version
COM'L
SA
LA
MIL &
IND
SA
LA
COM'L
SA
LA
MIL &
IND
SA
LA
COM'L
SA
LA
MIL &
IND
SA
LA
COM'L
SA
LA
MIL &
IND
SA
LA
COM'L
SA
LA
MIL &
IND
SA
LA
7130X55
7140X55
Com'l, Ind
& Military
Typ. Max.
110 155
110 110
110 190
110 140
20 65
20 35
20 65
20 45
40 110
40 75
40 125
40 90
1.0 15
0.2 4
1.0 30
0.2 10
40 100
40 70
40 110
40 85
2689 tbl 06a
7130X100
7140X100
Com'l, Ind
& Military
Typ. Max. Unit
110 155 mA
110 110
110 190
110 140
20 55 mA
20 35
20 65
20 45
40 110 mA
40 75
40 125
40 90
1.0 15 mA
0.2 4
1.0 30
0.2 10
40 95 mA
40 70
40 110
40 80
NOTES:
2689 tbl 06b
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC , TQFP and STQFP packages only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
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관련 데이터시트

부품번호상세설명 및 기능제조사
IDT7130LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology
Integrated Device Technology

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