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NT5CC128M8DN 데이터시트 PDF




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부품번호 NT5CC128M8DN 기능
기능 1Gb DDR3 SDRAM
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NT5CC128M8DN 데이터시트, 핀배열, 회로
1Gb DDR3 SDRAM
NT5CB128M8DN / NT5CB64M16DP
NT5CC128M8DN / NT5CC64M16DP
Feature
1.5V ± 0.075V & 1.35V -0.067/+0.1V
(JEDEC Standard Power Supply)
VDD= VDDQ= 1.35V (1.283~1.45V )
Backward compatible to VDD= VDDQ= 1.5V
±0.075V
Supports DDR3L devices to be backward
compatible in 1.5V applications
The timing specification of high speed bin is
backward compatible with low speed bin
8 Internal memory banks (BA0- BA2)
Differential clock input (CK, )
Programmable Latency: 5, 6, 7, 8, 9,
10, 11, 12, 13, (14)
POSTED CAS ADDITIVE Programmable Additive
Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8n-bit prefetch architecture
Output Driver Impedance Control
Differential bidirectional data strobe
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS Compliance
Lead-Free and Halogen-Free
Packages:
78-Ball BGA for x8 components
96-Ball BGA for x16 components
Operation Temperture
Commerical grade (0℃≦TC95)
- BE, CF, DH, EJ, FK
Industial grade (-40℃≦TC95)
- CFI, DHI
DCC Version 1.1
01/ 2014
1
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.




NT5CC128M8DN pdf, 반도체, 판매, 대치품
1Gb DDR3 SDRAM
NT5CB128M8DN / NT5CB64M16DP
NT5CC128M8DN / NT5CC64M16DP
Fig. 1: Pin Configuration 78 balls BGA Package (x8)
< TOP View>
See the balls through the package
1
VSS
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
2
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD

BA0
A3
A5
A7

3
NC
DQ0
DQS

DQ4



BA2
A0
A2
A9
A13
x8
7
A NU/
B DM/TDQS
C DQ1
D VDD
E DQ7
F CK
G 
H A10/AP
J NC
K A12/
L A1
M A11
N NC
8
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VERFCA
BA1
A4
A6
A8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
DCC Version 1.1
01 / 2014
4
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

4페이지










NT5CC128M8DN 전자부품, 판매, 대치품
1Gb DDR3 SDRAM
NT5CB128M8DN / NT5CB64M16DP
NT5CC128M8DN / NT5CC64M16DP
Symbol
A12/
Type
Input
Function
Burst Chop: A12/is sampled during Read and Write commands to determine if
burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
ODT, (ODT0),
(ODT1)

Input
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR3/L SDRAM. When enabled, ODT is applied to each DQ, DQS, and
DM/TDQS, NU/ (when TDQS is enabled via Mode Register A11=1 in MR1) signal
for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are
programmed to disable RTT.
Active Low Asynchronous Reset: Reset is active when  is LOW, and inactive
when  is HIGH.  must be HIGH during normal operation.  is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for
DC high and 0.30V
DQ Input/output Data Inputs/Output: Bi-directional data bus.
DQL,
DQU,
DQS,(),
DQSL,(),
DQSU,(),
TDQS, ()
Data Strobe: output with read data, input with write data. Edge aligned with read data,
centered with write data. The data strobes DQS, DQSL, DQSU are paired with
Input/output differential signals , , , respectively, to provide differential pair signaling
to the system during both reads and writes. DDR3/L SDRAM supports differential data
strobe only and does not support single-ended.
Termination Data Strobe: TDQS/ is applicable for X8 DRAMs only. When
Output
enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination
resistance function on TDQS/ that is applied to DQS/. When disabled via
mode register A11=0 in MR1, DM/ will provide the data mask function and 
is not used. x16 DRAMs must disable the TDQS function via mode register A11=0 in
MR1.
NC - No Connect: No internal electrical connection is present.
VDDQ
Supply DQ Power Supply: 1.5V ± 0.075V or 1.35V -0.067/+0.1V
VDD Supply Power Supply: 1.5V ± 0.075V or 1.35V -0.067/+0.1V
VSSQ
Supply DQ Ground
Vss Supply Ground
VREFCA
Supply Reference voltage for CA
VREFDQ
Supply Reference voltage for DQ
ZQ Supply Reference pin for ZQ calibration.
Note: Input only pins (BA0-BA2, A0-A13, , , , , CKE, ODT, and ) do not supply termination.
DCC Version 1.1
01 / 2014
7
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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1Gb DDR3 SDRAM

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