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Número de pieza APA6003
Descripción 15W Stereo Class D Audio Power Amplifier
Fabricantes ANPEC 
Logotipo ANPEC Logotipo



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APA6003
15W Stereo Class D Audio Power Amplifier
Features
General Description
Supply Voltage is 4.5V ~ 24V
The APA6003 is a stereo, high efficiency, Class-D audio
Class D operation eliminates heat sink & reduce amplifier available in TSSOP-28P and QFN4x4-28 pins
power supply requirement
packages.
20,26, 32, 36, 4 steps gain setting
The Class-D power amplifier has higher efficiency com-
15W/ch into an 8Loads at 10% THD+N from a paring to the tradition Class-AB power amplifier. The fil-
16-V supply
ter free Class-D architecture eliminates the external low
10W/ch into 8Loads at 10% THD+N from a 12-V pass filters. The internal gain setting can minimum the
supply
external component counts, and for the flexible applica-
30W into a 4Mono Load at 10% THD+N from a tion the gain can be set to 4-step 20, 26, 32, 36dB by gain
16-V Supply
control pins (GAIN0 and GAIN1). The AGC function pro-
90% Efficient Class-D Operation Eliminates Need tects speaker from being out of its power rating but keeps
for Heat Sinks
acceptable performance.
External AGC function
The integration of Class-D power amplifier is a best so-
Adjustable switch frequency
lution for power efficiency and lower the total BOM costs.
Flow Through Pin Out Facilitates Easy Board Lay- The operating voltage is from 4.5V to 24V. The APA6003
out power amplifiers are capable of driving 15 W at VDD=16V
Robust Pin-to-Pin Short Circuit Protection and Ther- into 8speaker, and provides thermal and over-current
mal Protection with Auto Recovery Option
protections also can detection the DC that prevent to de-
Excellent THD+N / Pop-Free Performance
stroy the speaker voice coil.
Thermal and Over-Current Protections with Auto-
Recovery option
Dual Differential Inputs with MUX
TSSOP-28P with thermal pad packages
QFN4x4-28B with thermal pad packages
Applications
LCD Monitor
Consumer Audio Equipment
Simplified Application Circuit
Left
Channel
Input
Right
Channel
Input
APA6003
LINNA
LOUTP
LINN
LINP
LINPA
LOUTN
RINNA
RINN
RINP
RINPA
ROUTN
ROUTP
FERRITE
BEAD
FILTER
FERRITE
BEAD
FILTER
Left
Channel
Speaker
Right
Channel
Speaker
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. P.1 - Sep., 2015
1
www.anpec.com.tw

1 page




APA6003 pdf
APA6003
Stereo Mode
VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted).
S ymbol
Parameter
Test Conditions
Min.
APA6003
Typ.
Max.
Unit
VDD= 12V, TA=25°C
Po Output Power
THD+N
P SRR
S NR
Att shutdown
|VOS|
Vn
Total Harmonic
Distortion Pulse Noise
Power Supply
Rejection Ratio
Signal-to-noise ratio
Shutdown Attenuation
Offset Voltage
Noise Output Voltage
VDD=16
THD+N = 1%, FIN = 1KHz
VDD=16
THD+N = 10%, FIN =
1kHz,
VDD=16
FIN = 1kHz, PO= 6, RL = 4
RL = 4
RL = 4
RL=4,input AC-Ground,FIN=1kHz
Maximum output at THD+N<1%,
FIN=1kHz, AV=20dB, A-weighted
FIN = 1kHz, RL = 8Ω, Vin= 1Vrms
AV=20dB
Input AC ground,
With A-weighted Filter (AV=20dB)
- 28 -
W
- 35 -
-
0.05
-
%
- -50 -
- 90 - dB
- -100 -
- 15 -
mV
- 150 - µV (rms)
Mono Mode
VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted).
VDD=12V,TA=25°C
Symbol
Parameter
Po Output Power
THD+N
Crosstalk
Total Harmonic
Distortion Pulse Noise
Channel separation
Test Condition
VDD=16V
THD+N = 1%, FIN = 1KHz
RL = 8
VDD=16V
THD+N = 10%, FIN = 1KHz
RL = 8
VDD=16V
FIN = 1kHz, PO= 6W, RL = 4
VO=1Vrms, FIN = 1kHz, AV=20dB
PSRR
SNR
At tshutdown
|VOS|
Vn
Power Supply
Rejection Ratio
Signal-to-noise ratio
Shutdown Attenuation
Offset Voltage
Noise Output Voltage
RL=4,input AC-Ground,FIN=1kHz
Maximum output at THD+N<1%,
FIN=1kHz, AV=20dB, A-weighted
FIN = 1kHz, RL = 8Ω, Vin= 1Vrms
Vin = 0V, AV=20dB
Input AC ground,
With A-weighted Filter (AV=20dB)
Min.
-
-
-
APA6003
Typ.
8
9.5
0.05
Max.
-
-
-
- -90 -
Unit
W
%
- -70 -
dB
- 90 -
- -100 -
- 10 -
mV
- 170 - µV (rms)
Copyright © ANPEC Electronics Corp.
Rev. P.1 - Sep., 2015
5
www.anpec.com.tw

5 Page





APA6003 arduino
APA6003
Function Description
Class-D Operation
Output = 0
VOUTP
VOUTN
VOUT
(VOUTP-VOUTN)
IOUT
Output > 0
VOUTP
VOUTN
VOUT
(VOUTP-VOUTN)
IOUT
Output < 0
VOUTP
VOUTN
VOUT
(VOUTP-VOUTN)
IOUT
Figure1. The APA6003 Output Waveform
The APA6003 uses a modulation scheme that allows op-
eration without the classic LC reconstruction filter when
the amp is driving an inductive load. Each output is switch-
ing from 0 volts to the supply voltage. The VOUTP and VOUTN
are in phase with each other with no input so that there is
little or no current in the speaker. The duty cycle of VOUTP is
greater than 50% and VOUTN is less than 50% for positive
output voltages. The duty cycle of V is less than 50%
OUTP
and V is greater than 50% for negative output voltages.
OUTN
The voltage across the load sits at 0V throughout most of
the switching period,
reducing the switching current, which reduces any I2R
losses in the load.
Gain Setting Operation
Gain1
0
0
1
1
Gain0
0
1
0
1
Gain
20
26
32
36
Input Impedance
60k
30k
15k
9k
Table 1 : The Gain Setting
The APA6003s gain can be set by GAIN0, GAIN1. The
detail gain setting value is list at table 1.
Shutdown Operation
In order to reduce power consumption while not in use,
the APA6003 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
pin for APA6003. The trigger point between a logic high
and logic low level is typically 2.2V. It is best to switch
between ground and the supply voltage VDD to provide
maximum device performance. By switching the SD pin
to low level, the amplifier enters a low-consumption- cur-
rent state, IDD for APA6003 is in shutdown mode. On
normal operating, APA6003s SD pin should pull to high
level to keeping the IC out of the shutdown mode. The SD
pin should be tied to a definite voltage to avoid unwanted
state changes.
AGC Function Operation
The APA6003 provides the non-clipping Control, When
the output reaches the maximum power setting value,
the internal Programmable Gain Amplifier (PGA) will de-
crease the gain for prevent the output waveform clipping.
Using the AGC pin to set the non-clipping function and
limit the output power.
VP=5.6 x AGC voltage if AGC<2.5V
VCLAMP Supply
The VCLAMP is used to power the gates of the output full
bridge transistors. It can also be used to supply the AGC
voltage divider circuit. Add a 1µF capacitor to ground at
this pin.
Copyright © ANPEC Electronics Corp.
Rev. P.1 - Sep., 2015
11
www.anpec.com.tw

11 Page







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