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SiI9573 데이터시트, 핀배열, 회로
SiI9573 and SiI9575 Port Processor
Data Sheet
SiI-DS-1089-F
March 2016




SiI9573 pdf, 반도체, 판매, 대치품
SiI9573 and SiI9575 Port Processor
Data Sheet
Figures
Figure 1.1. Port Processor Application............................................................................................................................ 7
Figure 2.1. Functional Block Diagram ............................................................................................................................. 9
Figure 2.2. I2C Control Configuration ............................................................................................................................ 10
Figure 3.1. Test Point SBVCC5TP for SBVCC5 Measurement ......................................................................................... 18
Figure 3.2. Audio Crystal Schematic ............................................................................................................................. 23
Figure 4.1. IDCK Clock Duty Cycle ................................................................................................................................. 26
Figure 4.2. Control and Data Single-Edge Setup and Hold TimesEDGE = 1 ............................................................... 26
Figure 4.3. Control and Data Single-Edge Setup and Hold TimesEDGE = 0 ............................................................... 26
Figure 4.4. Control and Data Dual-Edge Setup and Hold Times ....................................................................................27
Figure 4.5. Conditions for Use of RESET#.......................................................................................................................27
Figure 4.6. RESET# Minimum Timing.............................................................................................................................27
Figure 4.7. I2C Data Valid Delay (Driving Read Cycle Data) ........................................................................................... 28
Figure 4.8. I2C Data Setup Time .................................................................................................................................... 28
Figure 4.9. I2S Input Timing .......................................................................................................................................... 28
Figure 4.10. S/PDIF Input Timing .................................................................................................................................. 28
Figure 4.11. I2S Output Timing...................................................................................................................................... 29
Figure 4.12. S/PDIF Output Timing ............................................................................................................................... 29
Figure 4.13. MCLK Timing ............................................................................................................................................. 29
Figure 4.14. SPI Flash Memory Timing ......................................................................................................................... 30
Figure 5.1. Pin Diagram (Top View)............................................................................................................................... 31
Figure 6.1. Standby Power Supply Diagram .................................................................................................................. 40
Figure 6.2. VS Insertion in Active Space........................................................................................................................ 44
Figure 6.3. L/R and Active Space Indicators Output on GPIO Pins ................................................................................ 45
Figure 6.4. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 0).................................................................47
Figure 6.5. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 1).................................................................47
Figure 6.6. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ........................................................................................ 48
Figure 6.7. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ........................................................................................ 49
Figure 6.8. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ...................................................................................... 49
Figure 6.9. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ...................................................................................... 49
Figure 6.10. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ........................................................... 50
Figure 6.11. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ........................................................... 51
Figure 6.12. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ......................................................... 51
Figure 6.13. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ......................................................... 51
Figure 6.14. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................... 52
Figure 6.15. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................... 53
Figure 6.16. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 54
Figure 6.17. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 54
Figure 6.18. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 55
Figure 6.19. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 56
Figure 6.20. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ...........................................................57
Figure 6.21. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ...........................................................57
Figure 6.22. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 58
Figure 6.23. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 58
Figure 6.24. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 59
Figure 6.25. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 59
Figure 6.26. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) .............................................. 60
Figure 6.27. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 1) .............................................. 61
Figure 6.28. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 62
Figure 6.29. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 62
Figure 6.30. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 63
Figure 6.31. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 64
Figure 6.32. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) .................... 65
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 SiI-DS-1089-F

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SiI9573 전자부품, 판매, 대치품
1. General Description
The Lattice Semiconductor SiI9573 and SiI9575 Port
Processor is the latest generation HDMI® port
processor targeted at audio video receivers (AVR),
Home Theater in a Box (HTiB), and Digital TVs (DTVs).
The port processor has many innovative features such
as InstaPort®, InstaPrevue, Mobile High-Definition Link
(MHL®), ViaPort Matrix Switch (the SiI9575 device only),
and Audio Return Channel (ARC) technology.
The two devices are the same except where noted.
SiI957n is used throughout this document to refer to
both devices.
The SiI957n port processor offers an extensive set of
audio features including audio extraction and insertion.
Audio from the active HDMI input is sent to the main
or subaudio output port. High-Bitrate (HBR) audio is
supported on the main audio output port. Additionally,
a 2-channel I2S or an S/PDIF input receives PCM or bit
stream audio from an audio DSP or a DTV SoC, and
output to either the main or sub-HDMI output, or
both.
The SiI957n port processor supports two independent
ARC transceivers. Each ARC transceiver is configurable
as an ARC receiver or transmitter. As an ARC receiver in
an AVR or HTiB design, either the Tx0 or Tx1 HDMI
output can receive an ARC signal from a DTV. As an ARC
transmitter in a DTV design, the ARC signal can be
transmitted out of the two of the six Rx HDMI inputs,
which are designated as ARC-capable, to an AVR or
soundbar.
SiI9573 and SiI9575 Port Processor
Data Sheet
The MHL to HDMI bridge function is available on two
input ports; this allows consumers to attach their
mobile devices to the AVR or DTV and view high
definition content while the AVR or DTV charges the
mobile device battery.
The SiI9575 device supports ViaPort Matrix Switch.
While the main HDMI output selects one of the HDMI
inputs, the second HDMI output can select another
HDMI input or parallel video input. This is ideal for AVR
Zone 2 support or PIP/POP function in DTV.
1.1. HDMI Inputs and Outputs
Six HDMI input ports support 300 MHz
simultaneously
Two HDMI output ports that support 300 MHz
simultaneously
TMDS™ cores run up to 3.0 Gb/s
HDMI, MHL, HDCP, and DVI compatible
Supports video resolutions up to 4K × 2K @ 30 Hz,
8-bit, 1080p @ 60 Hz, 12-bit or 720p/1080i @ 120
Hz, 12-bit
Supports 4K × 2K 50P/60P FPS when pixel format is
YCb Cr 4:2:0.
Supports all the mandatory and some optional 3D
formats up to 300 MHz
MHL support up to1080p @ 24 Hz on two input
ports
Pre-programmed with HDCP keys
Repeater function supports up to 127 devices
Figure 1.1. Port Processor Application
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
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관련 데이터시트

부품번호상세설명 및 기능제조사
SiI9573

Port Processor

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SiI9575

Port Processor

Lattice
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