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부품번호 NB3H60113G 기능
기능 3.3V / 2.5V Programmable OmniClock Generator
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NB3H60113G 데이터시트, 핀배열, 회로
NB3H60113G
3.3 V / 2.5 V Programmable
OmniClock Generator
with Single Ended (LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/ HCSL/CML)
Outputs
www.onsemi.com
The NB3H60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS/LVTTL) reference clock as input. It
WDFN8
CASE 511AT
generates either three single ended (LVCMOS/LVTTL) outputs, or
one single ended output and one differential
MARKING DIAGRAM
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
1
H0MG
G
H0 = Specific Device Code
M = Date Code
G = Pb−Free Device
(Note: Microdot may be in either location)
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
ORDERING INFORMATION
crystal.
See detailed ordering and shipping information on page 21 of
this data sheet.
Features
Member of the OmniClock Family of Programmable Clock
Generators
Operating Power Supply: 3.3 V ± 10%, 2.5 V ± 10%
I/O Standards
Inputs: LVCMOS/LVTTL, Fundamental Mode
Crystal
Outputs: LVCMOS/LVTTL
Outputs: LVPECL, LVDS, CML and HCSL
3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
Power Saving mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 8−Pin WDFN
These are Pb−Free Devices
Crystal: 3 MHz to 50 MHz
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
Programmable Internal Crystal Load Capacitors
Programmable Output Drive Current for Single Ended
Outputs
Typical Applications
eBooks and Media Players
Smart Wearables, Portable Medical and Industrial
Equipment
Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NB3H60113G/D




NB3H60113G pdf, 반도체, 판매, 대치품
NB3H60113G
FUNCTIONAL DESCRIPTION
The NB3H60113G is a 3.3 V / 2.5 V programmable, single
ended / differential clock generator, designed to meet the
clock requirements for consumer and portable markets. It
has a small package size and it requires low power during
operation and while in standby. This device provides the
ability to configure a number of parameters as detailed in the
following section. The One−Time Programmable memory
allows programming and storing of one configuration in the
memory space.
3.3V/2.5V
R (optional)
0.1 mF 0.01 mF
Crystal or
Reference
Clock input
XIN/CLKIN
VDD
XOUT
NB3H60113G
PD#
CLK2
Single Ended Clock
CLK1
Single Ended Clocks
GND CLK0
OR
Differential Clock
LVPECL/LVDS/
HCSL/CML
Figure 3. Power Supply Noise Suppression
Power Supply
Device Supply
The NB3H60113G is designed to work with a 3.3 V/2.5 V
VDD power supply. For VDD operation of 1.8 V, refer to
NB3V60113G datasheet. In order to suppress power supply
noise it is recommended to connect decoupling capacitors of
0.1 mF and 0.01 mF close to the VDD pin as shown in
Figure 3.
Clock Input
Input Frequency
The clock input block can be programmed to use a
fundamental mode crystal from 3 MHz to 50 MHz or a
single ended reference clock source from 3 MHz to
200 MHz. When using output frequency modulation for
EMI reduction, for optimal performance, it is recommended
to use crystals with frequency more than 6.75 MHz as input.
Crystals with ESR values of up to 150 W are supported.
When using a crystal input, it is important to set crystal load
capacitor values correctly to achieve good performance.
Programmable Crystal Load Capacitors
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitor
can be programmed to any value between 4.36 pF and
20.39 pF with a step size of 0.05 pF. Refer to Table 3 for
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal –
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. These will be
bypassed when using an external reference clock.
Automatic Gain Control (AGC)
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of the power dissipation in the crystal; avoids
over driving the crystal and thus extending the crystal life.
In order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
www.onsemi.com
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NB3H60113G 전자부품, 판매, 대치품
NB3H60113G
Table 5. ATTRIBUTES
Characteristic
ESD Protection Human Body Model
Internal Input Default State Pull up/ down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
2 kV
50 kW
MSL1
UL 94 V−0 @ 0.125 in
130 k
Table 6. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
Parameter
Rating
Unit
VDD
Positive power supply with respect to Ground
−0.5 to +4.6
V
VI
TA
TSTG
TSOL
qJA
Input Voltage with respect to chip ground
Operating Ambient Temperature Range (Industrial Grade)
Storage temperature
Max. Soldering Temperature (10 sec)
Thermal Resistance (Junction−to−ambient)
(Note 3)
0 lfpm
500 lfpm
−0.5 to VDD + 0.5
−40 to +85
−65 to +150
265
129
84
V
°C
°C
°C
°C/W
°C/W
qJC Thermal Resistance (Junction−to−case)
35 to 40
°C/W
TJ Junction temperature
125 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
Table 7. RECOMMENDED OPERATION CONDITIONS
Symbol
VDD
Parameter
Core Power Supply Voltage
Condition
3.3 V operation
2.5 V operation
Min Typ Max Unit
2.97 3.3 3.63
2.25 2.5 2.75
V
CL Clock output load capacitance for
LVCMOS/ LVTTL clock
fout < 100 MHz
fout 100 MHz
15 pF
5 pF
fclkin
Crystal Input Frequency
Reference Clock Frequency
Fundamental Crystal
Single ended clock Input
3
3
50 MHz
200
CX XIN / XOUT pin stray Capacitance
Note 4
4.5 pF
CXL Crystal Load Capacitance
10 pF
ESR
Crystal ESR
150 W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. The XIN / XOUT pin stray capacitance needs to be subtracted from crystal load capacitance (along with PCB and trace capacitance) while
selecting appropriate load for the crystal in order to get minimum ppm error.
www.onsemi.com
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부품번호상세설명 및 기능제조사
NB3H60113G

3.3V / 2.5V Programmable OmniClock Generator

ON Semiconductor
ON Semiconductor

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