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AD5681R 데이터시트 PDF




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부품번호 AD5681R 기능
기능 Tiny 16-/14-/12-Bit SPI nanoDAC+
제조업체 Analog Devices
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AD5681R 데이터시트, 핀배열, 회로
Data Sheet
Tiny 16-/14-/12-Bit SPI nanoDAC+, with
±2 (16-Bit) LSB INL and 2 ppm/°C Reference
AD5683R/AD5682R/AD5681R/AD5683
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
Independent logic supply: 1.8 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
The AD5683R/AD5682R/AD5681R/AD5683, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the AD5683, include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The
AD5683R/AD5682R/AD5681R/AD5683 contain a power-down
mode that reduces the current consumption of the device to 2 µA
(maximum) at 5 V and provides software selectable output loads
while in power-down mode.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
Some devices also include asynchronous RESET pin and VLOGIC
pin options, allowing 1.8 V compatibility.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
LDAC
RESET
FUNCTIONAL BLOCK DIAGRAM
VLOGIC*
VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
16-/14-/12-BIT
DAC
AD5683R/
AD5682R/
AD5681R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
*NOT AVAILABLE IN ALL THE MODELS
SYNC SCLK SDI SDO*
GND
Figure 1. AD5683R/AD5682R/AD5681R MSOP
(For more information, see the Functional Block Diagrams—LFCSP section.)
Table 1. Single-Channel nanoDAC+ Portfolio
Interface Reference 16-Bit
14-Bit
SPI
Internal
AD5683R AD5682R
External
AD5683
I2C
Internal
AD5693R AD5692R
External
AD5693
12-Bit
AD5681R
AD5691R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5683R/AD5683 (16-bit): ±2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
3. Two Package Options.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5681R pdf, 반도체, 판매, 대치품
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.8 − 10% to 5 V + 10%, −40°C < TA < +105°C, unless
otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
AD5683R
Resolution
Relative Accuracy, INL
A Grade
B Grade
Differential Nonlinearity, DNL
AD5683
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
AD5682R
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
AD5681R
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error, TUE
Min
16
16
14
12
Zero-Code Error Drift
Offset Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio, PSRR
OUTPUT CHARACTERISTICS
Output Voltage Range
Capacitive Load Stability
0
0
Resistive Load
Load Regulation
1
Short-Circuit Current
Load Impedance at Rails2
20
Typ Max Unit Test Conditions/Comments
Bits
LSB
±8 LSB
±2 LSB Gain = 2
±3 Gain = 1
±1 LSB Guaranteed monotonic by design
Bits
±2 LSB Gain = 2
±3 LSB Gain =1
±1 LSB Guaranteed monotonic by design
Bits
±1 LSB
±1 LSB Guaranteed monotonic by design
Bits
±1 LSB
±1 LSB Guaranteed monotonic by design
1.25 mV
All 0s loaded to DAC register
±1.5 mV
±0.075 % of FSR All 1s loaded to DAC register
±0.05
% of FSR
±0.16
% of FSR Internal reference, gain = 1
±0.14
% of FSR Internal reference, gain = 2
±0.075 % of FSR External reference, gain = 1
±0.06
% of FSR External reference, gain = 2
±1 µV/°C
±1 µV/°C
±1 ppm/°C
0.2
mV/V
DAC code = midscale; VDD = 5 V ± 10%
VREF V
Gain = 1
2 × VREF
V
Gain = 2
2 nF RL = ∞
10 nF RL = 2 kΩ
kΩ CL = 0 µF
10 µV/mA 5 V, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA
10 µV/mA 3 V, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA
30 50
mA
20 Ω
Rev. C | Page 4 of 28

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AD5681R 전자부품, 판매, 대치품
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Timing and Circuit Diagrams
SCLK
t4
t9
t2
t8 t3
SYNC
t1
SDI DB23 DB22 DB21 DB20
t7
t11
t5
t6
DB2 DB1 DB0
t17
SDO
LDAC
RESET
VOUT
DB23 DB22 DB21 DB20
t10
DB2
DB1
t12
DB0
t13
t15
t16
t14
t18
Figure 4. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note)
200µA
IOL
TO OUTPUT
PIN CL
90pF
VOH (MIN)
200µA
IOH
Figure 5. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. C | Page 7 of 28

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AD5681R

Tiny 16-/14-/12-Bit SPI nanoDAC+

Analog Devices
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