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NT5DS128M4CS 데이터시트 PDF




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부품번호 NT5DS128M4CS 기능
기능 512Mb DDR SDRAM
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NT5DS128M4CS 데이터시트, 핀배열, 회로
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Features
• DDR 512M bit, Die C, based on 90nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.6V ± 0.1V (DDR400)
• VDD = VDDQ = 2.5V ± 0.2V (DDR333)
• RoHS compliance
Description
Die C of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 90 nm design process.
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
REV 1.0
Dec 2007
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.




NT5DS128M4CS pdf, 반도체, 판매, 대치품
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ3
NC
DQ2
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
128 X 4
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ0
NC
DQ1
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/
AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
REV 1.0
Dec 2007
4
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

4페이지










NT5DS128M4CS 전자부품, 판매, 대치품
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Block Diagram (128Mb x 4)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
15 13
13
A0-A12,
BA0, BA1
15
2
2
12
Column-Address
Counter/Latch
Bank1 Bank2 Bank3
CK, CK
DLL
8192
Bank0
MAermraoyry
(8192 x 2048 x 8)
Sense Amplifiers
I/O Gating
DM Mask Logic
2(0x84)8
Column
Decoder
11
COL0
1
8
8
8
Data
4
4
4
GeDneQraStor
COL0 Input
Register
Write Mask 1
1
FIFO
Driv&ers
2
8
colukt cinlk Data
1
4
4
1
4
4
1
DQS
1
4
CK, COL0
CK
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
REV 1.0
Dec 2007
7
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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NT5DS128M4CG

512Mb DDR SDRAM

Nanya Techology
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NT5DS128M4CG

512Mb DDR SDRAM

Nanya Techology
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