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부품번호 | 5P49EE802 기능 |
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기능 | Low-power Clock Generator | ||
제조업체 | Integrated Device Technology | ||
로고 | |||
전체 28 페이지수
VersaClock® Low-power Clock Generator
5P49EE802
DATASHEET
Description
The 5P49EE802 is a programmable clock generator intended
for low power, battery operated consumer applications. There
are four internal PLLs, each individually programmable,
allowing for up to eight different output frequencies. The
frequencies are generated from a single reference clock. The
reference clock can come from either a TCXO or fundamental
mode crystal. An additional 32kHz crystal oscillator is
available to provide a real time clock or non-critical
performance MHz processor clock.
The 5P49EE802 can be programmed through the use of the
I2C interfaces. The programming interface enables the device
to be programmed when it is in normal operation or what is
commonly known as in system programmable. An internal
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate four
unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the PLL
response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the PLLs.
The device is specifically designed to work with display
applications to ensure that the spread profile remains
consistent for each HSYNC in order to reduce ROW noise. It
also may operate in standard spread spectrum mode.
There are total seven 8-bit output dividers. Outputs are
LVCMOS. The outputs are connected to the PLLs via the
switch matrix. The switch matrix allows the user to route the
PLL outputs to any output bank. This feature can be used to
simplify and optimize the board layout. In addition, each
output's slew rate and enable/disable function can be
programmed.
Target Applications
• Smart Mobile Handset
• Personal Navigation Device (PND)
• Camcorder
• DSC
• Portable Game Console
• Personal Media Player
Features
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I2C EEPROM master interface
• FAST (400kHz) mode I2C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
• Output Frequency Ranges: kHz to 120 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock with
no visible artifacts
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– 3 independent adjustable VDDO groups
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
• Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
• 1.8V VDD Core Voltage
• Available in 28 pin 4x4mm QFN packages
• -40 to +85°C Industrial Temp operation
5P49EE802 REVISION P 04/01/16
1
©2016 Integrated Device Technology, Inc.
5P49EE802 DATASHEET
Pin Name
VDD
VDD
OUT0
VDDO3
SCLK
OUT6B
OUT6A
SDA
VDD
VDD
GND
XIN/ REF
XOUT
Pin #
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O Pin Type
Pin Description
Power Device power supply. Connect to 1.8V.
Power Device power supply. Connect to 1.8V.
O Adjustable Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT5.
I LVTTL I2C clock. Logic levels set by VDDO1. 5V tolerant.
O Adjustable Configurable clock output 6B. Output voltage levels are
controlled by VDDO1.
O Adjustable Configurable clock output 6A. Output voltage levels are
controlled by VDDO1.
I/O LVTTL Bidirectional I2C data. Logic levels set by VDDO1. 5V tolerant.
Power Device power supply. Connect to 1.8V.
Power Device power supply. Connect to 1.8V.
Power Connect to Ground.
I LVTTL MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum clock input voltage is 1.8V.
O LVTTL MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above. Always
completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default factory configuration OUT4=buffered reference output & OUT2=32.768KHz. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
Ideal Power Up Sequence
1) VDD and VDDx must come up first, followed by VDDO
2) VDDO1 must come up within 1ms after VDD and VDDX come up
3) VDDO2/3 must be equal to, or lower than, VDDO1
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2/3 have approx. same ramp rate
V
VDDO1
VDD, VDDx
VDDO2, VDDO3
Ideal Power Down Sequence
1) VDDO must drop first, followed by VDD and VDDx
2) VDD and VDDx must come down within 1ms after VDDO1 comes down
3) VDDO2/3 must be equal to, or lower than, VDDO1
4) VDD and VDDx have approx. the same ramp rate
5) VDDO1 and VDDO2/3 have approx. same ramp rate
V
VDDO1
VDDO2, VDDO3
VDD, VDDx
1 ms
t
1 ms
t
VERSACLOCK® LOW-POWER CLOCK GENERATOR
4
REVISION P 04/01/16
4페이지 VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship
5P49EE802 DATASHEET
Integer multiple of HSYNC periods
VSYNC
HSYNC
DOT_CLK
X/2
X
X = Number of cycles of DOT_CLK per HSYNC period.
X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls.
Modulation
Rate
X/2
X
Loop Filter
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from the
jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low jitter
generation. The specific loop filter components that can be
programmed are the resistor via the RZ[4:0] bits, zero
capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0]
bits, and the charge pump current via the IP#[2:0] bits.
The following equations govern how the loop filter is set:
Zero capacitor (Cz) = 280pF
Pole capacitor (Cp) = 30pF
Charge pump (Ip) = IP#[2:0] uA
VCO gain (KVCO) = 350MHz/V * 2
REVISION P 04/01/16
7
VERSACLOCK® LOW-POWER CLOCK GENERATOR
7페이지 | |||
구 성 | 총 28 페이지수 | ||
다운로드 | [ 5P49EE802.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
5P49EE802 | Low-power Clock Generator | Integrated Device Technology |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |