MX25L3205
FEATURES
Macronix NBitTM Memory Family
32M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 33,554,432 x 1 bit structure
• 64 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 64s/chip (typical)
- Acceleration mode:
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 51s/chip
(typical)
• Low Power Consumption
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
• Additional 4Kb sector independent from main memory
for parameter storage to eliminate EEPROM from
system
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO/PO7
- Serial Data Output or Parallel mode Data output/input
• WP#/ACC Pin
- Hardware write protection and Program/erase accel-
eration
• HOLD# pin
- pause the chip without diselecting the chip (not for
paralled mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
• PO0~PO6
- for parallel mode data output/input
• PACKAGE
- 16-pin SOP (300mil)
P/N: PM1169
REV. 1.0, JUL. 15, 2005
1
MX25L3205
DATA PROTECTION
The MX25L3205 are designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of
specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down
transition or system noise.
• Power-On Reset and an internal timer (tPUW) can
provide protection against inadvertant changes while
the power supply is outside the operating specification.
• Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
• All instructions that modify data must be preceded by
a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit . This bit is returned to its reset
state by the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Chip Erase (CE) instruction completion
• The Block Protect (BP2, BP1, BP0) bits allow part of
the memory to be configured as readonly. This is the
Software Protected Mode (SPM).
• The Write Protect (WP#) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status Register
Write Disable (SRWD) bit to be protected. This is the
Hardware Protected Mode (HPM).
• In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protec-
tion from inadvertent Write, Program and Erase in-
structions, as all instructions are ignored except one
particular instruction (the Release from Deep
Powerdown instruction).
• To avoid unexpected changes by system power supply
transition, the Power-On Reset and an internal timer
(tPUW) can protect the device.
• Before the Program, Erase, and Write Status Register
execution, instruction length will be checked on follow-
ing the clock pulse number to be multiple of eight base.
• Write Enable (WREN) instruction must set to Write
Enable Latch (WEL) bit before writing other instructions
to modify data. The WEL bit will return to reset state by
following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Chip Erase (CE) instruction completion
• The Software Protected Mode (SPM) use (BP2, BP1,
BP0) bits to allow part of memory to be protected as
read only.
• The Hardware Protected Mode (HPM) use WP# to
protect the (BP2, BP1, BP0) bits and SRWD bit.
• Deep-Power Down Mode also protects the device by
ignoring all instructions except Release from Deep-
Power Down (RDP) instruction and RES instruction.
P/N: PM1169
REV. 1.0, JUL. 15, 2005
4
