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ICX267AK 데이터시트 PDF




Sony에서 제조한 전자 부품 ICX267AK은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ICX267AK 자료 제공

부품번호 ICX267AK 기능
기능 Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor
제조업체 Sony
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ICX267AK 데이터시트, 핀배열, 회로
ICX267AK
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX267AK is a diagonal 8mm (Type 1/2) interline
CCD solid-state image sensor with a square pixel array
and 1.45M effective pixels. Progressive scan allows all
pixels' signals to be output independently. Also, the
adoption of high frame rate readout mode supports
30 frames per second. This chip features an electronic
shutter with variable charge-storage time which
makes it possible to realize full-frame still image
without a mechanical shutter. High resolution and
high color reproductivity are achieved through the use
of R, G, B primary color mosaic filters. Further, high
sensitivity and low dark current are achieved through
the adoption of HAD (Hole-Accumulation Diode)
sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
20 pin DIP (Plastic)
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High horizontal and vertical resolution (both approx.
800TV-lines) still image without a mechanical shutter.
Supports high frame rate readout mode
(effective 512 lines output, 30 frames/s)
Square pixel
Horizontal drive frequency: 28.636MHz
No voltage adjustments
(reset gate and substrate bias are not adjusted.)
R, G, B primary color mosaic filters on chip
High resolution, high color reproductivity,
high sensitivity, low dark current
Low smear, excellent antiblooming characteristics
Continuous variable-speed shutter
Pin 1
V
2
Pin 11
H
40
Optical black position
(Top view)
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8mm (Type 1/2)
Total number of pixels: 1434 (H) × 1050 (V) approx. 1.50M pixels
Number of effective pixels: 1392 (H) × 1040 (V) approx. 1.45M pixels
Number of active pixels: 1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)
Chip size:
7.60mm (H) × 6.20mm (V)
Unit cell size:
4.65µm (H) × 4.65µm (V)
Optical black:
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Number of dummy bits: Horizontal 20
Vertical 3
Substrate material:
Silicon
2
8
Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99947A33




ICX267AK pdf, 반도체, 판매, 대치품
ICX267AK
Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Power Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
VL
φSUB
φRG
14.55
15.0
1
2
2
15.45
V
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Power supply current
Symbol Min. Typ. Max. Unit Remarks
IDD 7.7 mA
Clock Voltage Conditions
Item Symbol
Readout clock voltage VVT
VVH02A
VVH1, VVH2A,
VVH2B, VVH3
VVL1, VVL2A,
VVL2B, VVL3
Vertical transfer clock
voltage
Vφ1, Vφ2A,
Vφ2B, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
Horizontal transfer
clock voltage
VφH
VHL
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
Min.
14.55
–0.05
–0.2
–8.4
7.6
4.75
–0.05
3.0
22.15
Typ.
15.0
0
Max.
Unit
Waveform
diagram
Remarks
15.45 V
1
0.05 V
2 VVH = VVH02A
0 0.05 V
2
–8.0 –7.6 V
2 VVL = (VVL1 + VVL3)/2
8.0 8.4 V
0.1 V
0.9 V
1.3 V
1.0 V
0.9 V
5.0 5.25 V
0 0.05 V
3.3 5.5 V
0.4 V
0.5 V
23.0 23.85 V
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
4
4 Low-level coupling
4 Low-level coupling
5
–4–

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ICX267AK 전자부품, 판매, 대치품
ICX267AK
(3) Horizontal transfer clock waveform
tr twh
Hφ2
90%
tf
10%
Hφ1
VφH
VφH
2
two
VCR
twl
VHL
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr twh
tf
RG waveform
VRGH
VRGLH
VRGLL
VRGLm
VφRG
Point A
twl
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL.
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
10%
VSUB
0%
(A bias generated within the CCD)
VφSUB
tr twh
–7–
tf
φM
φM
2

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