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ALT6720 데이터시트 PDF




ANADIGICS에서 제조한 전자 부품 ALT6720은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ALT6720 자료 제공

부품번호 ALT6720 기능
기능 LTE Linear PAM
제조업체 ANADIGICS
로고 ANADIGICS 로고


ALT6720 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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ALT6720 데이터시트, 핀배열, 회로
FEATURES
• LTE Compliant
• 4th Generation HELPTM technology
• High Efficiency (LTE MPR = 0 dB):
• 36 % @ POUT = +27.5 dBm
• 23 % @ POUT = +16 dBm
• 16 % @ POUT = +7 dBm
Low Quiescent Current: 3 mA
Low Leakage Current in Shutdown Mode: <5 µA
Internal Voltage Regulator
Integrated “daisy chainable” directional coupler
with CPLIN and CPLOUT port.
Internal DC block on IN/OUT RF ports
Optimized for a 50 System
1.8 V Control Logic
RoHS Compliant Package, 260 oC MSL-3
ALT6720
HELP4TM E800 (Band 20)
LTE Linear PAM
Data Sheet - Rev 2.3
ALT6720
M45 Package
10 Pin 3 mm x 3 mm x 1 mm
Surface Mount Module
APPLICATIONS
Band 20 LTE Wireless Devices
PRODUCT DESCRIPTION
The ALT6720 HELP4TM PA is a 4th generation HELPTM
product for LTE devices operating in E800 MHz Band
20. This PA incorporates ANADIGICS’ HELP4TM
technology to deliver exceptional efficiency at low
power levels and low quiescent current without the
need for external voltage regulators or converters.
The device is manufactured using advanced InGaP-
PlusTM HBT technology offering state-of-the-art
reliability, temperature stability, and ruggedness.
Three selectable bias modes that optimize efficiency
for different output power levels and a shutdown
mode with low leakage current increase handset
talk and standby time. A “daisy chainable” directional
coupler is integrated in the module, thus eliminating
the need of an external coupler. The self-contained
3 mm x 3 mm x 1 mm surface mount package
incorporates matching networks optimized for output
power, efficiency, and linearity in a 50 system.
VBATT
RFIN
VMODE2
VMODE1
VEN
1
2
3
4
5
GND at Slug (pad)
10 VCC
CPL
9 RFOUT
Bias Control
Voltage Regulation
8 CPLIN
7 GND
6 CPLOUT
Figure 1: Block Diagram
03/2012




ALT6720 pdf, 반도체, 판매, 대치품
ALT6720
Table 4: Electrical Specifications - LTE Operation (MPR = 0 waveform, 10 MHZ QPSK, 12 RB’s)
(TC = +25 °C, VCC = +3.4 V, VBATT = +3.4 V, VEN = +1.8 V, 50 system)
PARAMETER
MIN TYP
MAX
UNIT
COMMENTS
POUT
VMODE1
VMODE2
Gain
27.5
17
10
30
20
13
33.5
23
16
+27.5 dBm
dB +16 dBm
+7 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
LTE to LTE, E-UTRA
- -39 -35
+27.5 dBm
- -39 -35 dBc +16 dBm
- -40 -35
+7 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
UTRA ACLR1
- -40 -36
+27.5 dBm
- -39 -36 dBc +16 dBm
- -41 -36
+7 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
UTRA ACLR2
- -60 -40
+27.5 dBm
- -60 -40 dBc +16 dBm
- -60 -40
+7 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
Power-Added Efficiency (1)
Quiescent Current (Icq)
Low Bias Mode
32 36
19 23
13 16
- 2.5
-
-
-
4
+27.5 dBm
% +16 dBm
+7 dBm
mA through VCC pin
0V
1.8 V
1.8 V
0V
0V
1.8 V
1.8 V 1.8 V
Mode Control Current
- 0.07 0.15 mA through VMODE pins, VMODE1,2 = +1.8 V
Enable Current
BATT Current
Leakage Current
Noise Power
- 0.03 0.1
mA through VEN pin
- 0.8 1.5 mA through VBATT pin, VMODE1,2 = +1.8 V
- <5
10
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN = 0 V, VMODE1,2 = 0 V
- -132
- -138
- -143
- 791 - 821 MHz
- dBm/Hz GPS Band, 1574 - 1577 MHz
- ISM Band, 2400 - 2483.5 MHz
Harmonics
2fo
3fo, 4fo
- -50
- -62
-
-
dBc POUT < +27.5 dBm
Coupling Factor
Directivity
- 20.5
- 20
-
-
dB
dB
Daisy Chain Insertion Loss
- <0.3
-
dB
698 - 2620 MHz
Pin 8 through 9, shutdown mode
Spurious Output Level
(all spurious outputs)
POUT < +27.5 dBm
-
-
-70
dBc
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
Load mismatch stress with
no permanent degradation or
failure
8:1
-
Notes:
(1) ACLR and Efficiency measured at 847 MHz.
-
VSWR Applies over full operating range
4 Data Sheet - Rev 2.3
03/2012

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ALT6720 전자부품, 판매, 대치품
ALT6720
PCB AND STENCIL DESIGN GUIDELINE
Figure 6: Recommended PCB Layout Information
7 Data Sheet - Rev 2.3
03/2012

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