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PDF 54LS16 Data sheet ( Hoja de datos )
| Número de pieza | 54LS16 | |
| Descripción | HEX INVERTER BUFFERS/DRIVERS | |
| Fabricantes | Texas | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 54LS16 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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• Converts TTL Voltage Levels to MOS
Levels
• High Sink-Current Capability
• Input Clamping Diodes Simplify System
Design
• Open-Collector Driver for Indicator Lamps
and Relays
• Package Options Include “Small Outline”
Packages, Ceramic Chip Carriers, and
Standard Plastic and Ceramic 300-mil DIPs
SN54LS06, SN54LS16, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020A – MAY 1990
SN54LS06, SN54LS16 . . . J PACKAGE
SN74LS06, SN74LS16 . . . D OR N PACKAGE
(T0P VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
description
These monolithic hex inverter buffers/drivers
feature high-voltage open-collector outputs to
interface with high-level circuits (such as MOS), or
for driving high-current loads, and are also
characterized for use as inverter buffers for driving
TTL inputs. The ′LS06 has a rated output voltage
of 30 V and the ′LS16 has a rated output voltage
of 15 V. The maximum sink current for the
SN54LS06 and SN54LS16 is 30 mA and the
SN74LS06 and SN74LS16 is 40 mA.
SN54LS06, SN54LS16 . . . FK PACKAGE
(T0P VIEW)
2A
3 2 1 20 19
4 18
6Y
NC 5
17 NC
2Y 6
16 5A
NC 7
15 NC
3A 8
14 5Y
9 10 11 12 13
These circuits are compatible with most TTL
families. Inputs are diode-clamped to minimize
transmission-effects, which simplifies design.
Typical power dissipation is 175 mW and average
propagation delay time is 8 ns.
NC – No internal connection
The SN54LS06 and SN54LS16 are characterized over the full military temperature range of – 55°C to 125°C.
The SN74LS06 and SN74LS16 are characterized for operation from 0°C to 70°C.
logic symbol†
1A 1
2A 3
3A 5
4A 9
5A 11
6A 13
2 1Y
4 2Y
6 3Y
8 4Y
10 5Y
12 6Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
Pin numbers shown are for D, J, and N packages.
logic diagram (positive logic)
1A 1
2 1Y
3
2A
4 2Y
3A 5
6 3Y
9
4A
8 4Y
5A 11
10 5Y
13
6A
12 6Y
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1990, Texas Instruments Incorporated
1
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet 54LS16.PDF ] | |
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