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ADSP-BF700 데이터시트 PDF




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부품번호 ADSP-BF700 기능
기능 Blackfin+ Core Embedded Processor
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ADSP-BF700 데이터시트, 핀배열, 회로
Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION
PERIPHERALS FEATURES
See Figure 1, Processor Block Diagram and Table 1, Processor
Comparison
MEMORY
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
SYSTEM CONTROL BLOCKS
EVENT
CONTROL
WATCHDOG
PERIPHERALS
1× TWI
8× TIMER
1× COUNTER
B
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
L2 MEMORY
512K BYTE
ROM
UP TO
1M BYTE SRAM
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
EXTERNAL
BUS
INTERFACES
MEMORY
PROTECTION
DYNAMIC MEMORY
CONTROLLER
SYSTEM FABRIC
OTP
MEMORY
HARDWARE
FUNCTIONS
ANALOG
SUB
SYSTEM
SYSTEM PROTECTION
CRYPTO ENGINE (SECURITY)
HADC
2× CAN
2× UART
SPI HOST PORT
2x QUAD SPI
1x DUAL SPI
GPIO
2× SPORT
1× MSI
(SD/SDIO)
1× PPI
STATIC MEMORY
CONTROLLER
3× MDMA
STREAMS
2× CRC
1× RTC
LPDDR
DDR2
16
1× USB 2.0 HS OTG
Figure 1. Processor Block Diagram
Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADSP-BF700 pdf, 반도체, 판매, 대치품
ADSP-BF700/701/702/703/704/705/706/707
BLACKFIN+ PROCESSOR CORE
As shown in Figure 1, the processor integrates a Blackfin+
processor core. The core, shown in Figure 2, contains two 16-bit
multipliers, one 32-bit multiplier, two 40-bit accumulators
(which may be used together as a 72-bit accumulator), two
40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit
shifter. The computation units process 8-, 16-, or 32-bit data
from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The core can perform two 16-bit by 16-bit multiply-accumu-
lates or one 32-bit multiply-accumulate in each cycle. Signed
and unsigned formats, rounding, saturation, and complex mul-
tiplies are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, divide primitives, saturation and rounding, and
sign/exponent detection. The set of video instructions include
byte alignment and packing operations, 16-bit and 8-bit adds
with clipping, 8-bit average operations, and 8-bit subtract/abso-
lute value/accumulate (SAA) operations. Also provided are the
compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If a second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
I2 L2 B2
I1 L1 B1
I0 L0 B0
M3
M2
M1
M0
DAG1
32
RAB
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD 32
LD1 32
LD0 32
32
32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
16
88
BARREL
40 SHIFTER
32
72
40 A0
32
DATA ARITHMETIC UNIT
ASTAT
16
88
40
A1
32
40
Figure 2. Blackfin+ Processor Core
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT
Rev. A | Page 4 of 116 | September 2015

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ADSP-BF700 전자부품, 판매, 대치품
ADSP-BF700/701/702/703/704/705/706/707
output enable and the input enable of a GPIO pin are both
active, the data signal before the pad driver is looped back to the
receive path for the same GPIO pin.
MEMORY ARCHITECTURE
The processor views memory as a single unified 4G byte address
space, using 32-bit addresses. All resources, including internal
memory, external memory, and I/O control registers, occupy
separate sections of this common address space. The memory
portions of this address space are arranged in a hierarchical
structure to provide a good cost/performance balance of some
very fast, low-latency core-accessible memory as cache or
SRAM, and larger, lower-cost and performance interface-acces-
sible memory systems. See Figure 3.
Internal (Core-Accessible) Memory
The L1 memory system is the highest-performance memory
available to the Blackfin+ processor core.
The core has its own private L1 memory. The modified Harvard
architecture supports two concurrent 32-bit data accesses along
with an instruction fetch at full processor speed which provides
high-bandwidth processor performance. In the core, a 64K byte
block of data memory partners with an 64K byte memory block
for instruction storage. Each data block is multibanked for effi-
cient data exchange through DMA and can be configured as
SRAM. Alternatively, 16K bytes of each block can be configured
in L1 cache mode. The four-way set-associative instruction
cache and the 2 two-way set-associative data caches greatly
accelerate memory access performance, especially when access-
ing external memories.
The L1 memory domain also features a 8K byte data SRAM
block which is ideal for storing local variables and the software
stack. All L1 memory is protected by a multi-parity-bit concept,
regardless of whether the memory is operating in SRAM or
cache mode.
Outside of the L1 domain, L2 and L3 memories are arranged
using a Von Neumann topology. The L2 memory domain is a
unified instruction and data memory and can hold any mixture
of code and data required by the system design. The L2 memory
domain is accessible by the Blackfin+ core through a dedicated
64-bit interface. It operates at SYSCLK frequency.
The processor features up to 1M byte of L2 SRAM, which is
ECC-protected and organized in eight banks. Individual banks
can be made private to any system master. There is also a
512K byte single-bank ROM in the L2 domain. It contains boot
code, security code, and general-purpose ROM space.
OTP Memory
The processor features 4 kB of one-time-programmable (OTP)
memory which is memory-map accessible. This memory stores
a unique chip identification and is used to support secure-boot
and secure operation.
0x FFFF FFFF -
PROCESSOR MEMORY MAP
Reserved
0x 9000 0000 -
0x 8000 0000 -
0x 7400 2000 -
0x 7400 0000 -
0x 7000 2000 -
0x 7000 0000 -
DDR2 or LPDDR Memory (256 MB)
Reserved
Static Memory Block 1 (8 KB)
Reserved
Static Memory Block 0 (8 KB)
Reserved
0x 4800 0000 -
0x 4000 0000 -
0x 3800 1000 -
0x 3800 0000 -
0x 2030 1000 -
0x 2030 0000 -
0x 2000 0000 -
0x 1FC0 0000 -
0x 11B0 2000 -
0x 11B0 0000 -
0x 11A1 0000 -
0x 11A0 C000 -
0x 11A0 0000 -
0x 1190 8000 -
0x 1190 4000 -
0x 1190 0000 -
0x 1180 8000 -
0x 1180 4000 -
0x 1180 0000 -
0x 0810 0000 -
0x 0800 0000 -
0x 0408 0000 -
0x 0401 0000 -
0x 0400 0000 -
0x 0000 0000 -
SPI2 Memory (128 MB)
Reserved
OTP Memory (4 KB)
Reserved
STM Memory (4 KB)
System MMR Registers (3 MB)
Core MMR Registers (4 MB)
Reserved
L1 Data Block C (8 KB)
Reserved
L1 Instruction SRAM/Cache (16 KB)
L1 Instruction SRAM (48 KB)
Reserved
L1 Data Block B SRAM/Cache (16 KB)
L1 Data Block B SRAM (16 KB)
Reserved
L1 Data Block A SRAM/Cache (16 KB)
L1 Data Block A SRAM (16 KB)
Reserved
L2 SRAM (1024 KB)
Reserved
L2 ROM (448 KB)
Boot ROM (64 KB)
Reserved
Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map
Rev. A | Page 7 of 116 | September 2015

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