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IS39LV010 데이터시트 PDF




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부품번호 IS39LV010 기능
기능 3.0 Volt-only CMOS Flash Memory
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IS39LV010 데이터시트, 핀배열, 회로
IS39LV512 / IS39LV010 / IS39LV040
512 Kbit / 1Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory
FEATURES
Single Power Supply Operation
- Low voltage range: 2.70 V - 3.60 V
• Memory Organization
- IS39LV512: 64K x 8 (512 Kbit)
- IS39LV010: 128K x 8 (1 Mbit)
- IS39LV040: 512K x 8 (4 Mbit)
• High Performance Read
- 70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
IS39LV512)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
- Build-in automatic program verification
- Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 µA CMOS standby current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
• Operation temperature range
- IS39LV512/010
-40oC~+85oC
- IS39LV040
0oC~+85oC
GENERAL DESCRIPTION
The IS39LV512/010/040 are 512 Kbit/1 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are designed
to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program
operations. The 12.0 Volt VPP power supply for program and erase operations are not required. The devices can
be programmed in standard EPROM programmers as well.
The memory array of I S39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -
consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory
area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in
others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The
devices can be progr ammed on a byte-by-byte basis after performing the erase operation.
The devices have a s tandard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
liossguicinagutthoemcahtiicpaellyrahs aen, dblleosckth, eorpsreocgtroarmemrainseg
voltage ramp-up and timing. The erase
command code into command register.
operation is
The internal
executed by
control logic
automatically handle s the erase voltage ramp-up and timing. The preprogramming on the array which has not
been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit
functions,
Polling on
tIh/Oe7pororgthree sTsoogrgcleomBipt loentioIn/Oo6f.
program
and
erase
operations
can
be
detected
by
reading
the
Data#
The IS39LV512/010/0 40 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
04/24/2013
1




IS39LV010 pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
IS39LV512 / IS39LV010 / IS39LV040
WE#
CE#
OE#
ERASE/PROGRAM
VOLTAGE
GENERATOR
HIGH V O L T A G E
SWITCH
I/O0-I/O7
I/O BUFFERS
COMMAND
REGISTER
A0-AMS
CE,OE LOGIC
DATA
LATCH
SENSE
AMP
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
DEVICE OPERATION
READ OPERATION
The access of IS39LV512/010/040 are similar to
EPROM. To read data, three control functions must
be satisfied:
• CE# is the chip enable and should be pulled low ( VIL ).
• OE# is the output enable and should be pulled low
( VIL).
• WE# is the write enable and should remains high (
VIH ).
PRODUCT IDENTIFICATION
The product identification mode can be used to identify
the manufacturer and the device through hardware or
software read ID operation. See Table 1 for pFLASH™
Manufacturer ID and Device ID. The hardware ID mode
is activated by applying a 12.0 Volt on A9 pin, typically
used by an external programmer for selecting the right
programming algorithm for the devices. Refer to Table
2 for Bus Operation Modes. The software ID mode is
activated by a three-bus-cycle command. See Table 3
for Software Command Definition.
BYTE PROGRAMMING
The programming is a four-bus-cycle operation and
the data is programmed into the devices (to a logical
“0”) on a byte-by-byte basis. See Table 3 for Software
Command Definition. A program operation is activated
by writing the three-byte command sequence followed
by program address and one byte of program data
into the devices. The addresses are latched on the
falling edge of WE# or CE# whichever occurs later,
and the data are latched on the rising edge of WE# or
CE# whichever occurs first. The internal control logic
automatically handles the internal programming volt-
ages and timing.
A data “0” can not be programmed back to a “1”. Only
erase operation can convert the “0”s to “1”s. The Data#
Polling on I/O7 or Toggle Bit on I/O6 can be used to
detect the progress or completion of a program cycle.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
04/24/2013
4

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IS39LV010 전자부품, 판매, 대치품
OPERATING MODES
IS39LV512 / IS39LV010 / IS39LV040
Table 2. Bus Operation Modes
Mode
Read
Write
Standby
Output Disable
Product Identifi-
cation Hardware
CE#
VIL
VIL
VIH
X
VIL
OE#
VIL
VIH
X
VIH
WE#
VIH
VIL
X
X
ADDRESS
X (1)
X
X
X
A2 - AMS (2) = X, A9 = VH (3), A1 = VIL, A0 = VIL
VIL VIH
A2 - AMS (2) = X, A9 = VH (3),
A1 = VIL, A0 = VIH
I/O
DOUT
DIN
High Z
High Z
Manufacturer ID
Device I
Notes:
1. X can be VIL, VIH or addresses.
2. AMS = Most significant address;
AMS = A15 for IS39LV512, A16 for IS39LV010, and
A18 for IS39LV040.
3. VH = 12.0 V ± 0.5 V.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
04/24/2013
7

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IS39LV010

3.0 Volt-only CMOS Flash Memory

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