|
|
PDF IS39LV040 Data sheet ( Hoja de datos )
| Número de pieza | IS39LV040 | |
| Descripción | 3.0 Volt-only CMOS Flash Memory | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS39LV040 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
IS39LV512 / IS39LV010 / IS39LV040
512 Kbit / 1Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.70 V - 3.60 V
• Memory Organization
- IS39LV512: 64K x 8 (512 Kbit)
- IS39LV010: 128K x 8 (1 Mbit)
- IS39LV040: 512K x 8 (4 Mbit)
• High Performance Read
- 70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
IS39LV512)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
- Build-in automatic program verification
- Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 µA CMOS standby current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
• Operation temperature range
- IS39LV512/010
-40oC~+85oC
- IS39LV040
0oC~+85oC
GENERAL DESCRIPTION
The IS39LV512/010/040 are 512 Kbit/1 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are designed
to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program
operations. The 12.0 Volt VPP power supply for program and erase operations are not required. The devices can
be programmed in standard EPROM programmers as well.
The memory array of I S39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -
consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory
area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in
others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The
devices can be progr ammed on a byte-by-byte basis after performing the erase operation.
The devices have a s tandard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
liossguicinagutthoemcahtiicpaellyrahs aen, dblleosckth, eorpsreocgtroarmemrainseg
voltage ramp-up and timing. The erase
command code into command register.
operation is
The internal
executed by
control logic
automatically handle s the erase voltage ramp-up and timing. The preprogramming on the array which has not
been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit
functions,
Polling on
tIh/Oe7pororgthree sTsoogrgcleomBipt loentioIn/Oo6f.
program
and
erase
operations
can
be
detected
by
reading
the
Data#
The IS39LV512/010/0 40 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
1
1 page  
DEVICE OPERATION (CONTINUED)
IS39LV512 / IS39LV010 / IS39LV040
CHIP ERASE
HARDWARE DATA PROTECTION
The entire memory array can be erased through a chip
erase operation. Pre-programs the devices are not
required prior to a chip erase operation. Chip erase
starts immediately after a six-bus-cycle chip erase
command sequence. All commands will be ignored
once the chip erase operation has started. The devices
will return to standby mode after the completion of chip
erase.
Hardware data protection protects the devices from un-
intentional erase or program operation. It is performed
in the following ways: (a) VCC sense: if VCC is below 1.8
V (typical), the write operation is inhibited. (b) Write
inhibit: holding any of the signal OE# low, CE# high, or
WE# high inhibits a write cycle. (c) Noise filter: pulses
of less than 5 ns (typical) on the WE# or CE# input will
not initiate a write operation.
SECTOR AND BLOCK ERASE
The memory array of IS39LV512/010/040 are organized
into uniform 4 Kbyte sectors. A sector erase operation
allows to erase any individual sector without affecting
the data in others. The memory array of IS39LV010/040,
excluding IS39LV512, are also organized into uniform
64 Kbyte blocks (sector group - consists of sixteen
adjacent sectors). A block erase operation allows to
erase any individual block. The sector or block erase
operation is similar to chip erase.
Table 1. Product Identification
Product Identification
Manufacturer ID
Device ID:
IS39LV512
Data
9Dh
1Bh
I/O7 DATA# POLLING
IS39LV010
1Ch
The IS39LV512/010/040 provide a Data# Polling fea-
ture to indicate the progress or completion of a program
and erase cycles. During a program cycle, an attempt
to read the devices will result in the complement of the
last loaded data on I/O7. Once the program operation
is completed, the true data of the last loaded data is
valid on all outputs. During a sector, block, or chip erase
cycle, an attempt to read the device will result a “0” on
I/O7. After the erase operation is completed, an attempt
to read the device will result a “1” on I/O7.
IS39LV040
3Eh
I/O6 TOGGLE BIT
The IS39LV512/010/040 also provide a Toggle Bit fea-
ture to detect the progress or completion of a program
and erase cycles. During a program or erase cycle, an
attempt to read data from the device will result a tog-
gling between “1” and “0” on I/O6. When the program
or erase operation is complete, I/O6 will stop toggling
and valid data will be read. Toggle bit may be accessed
at any time during a program or erase cycle.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
5
5 Page 
IS39LV512 / IS39LV010 / IS39LV040
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data 55h
to
Address 2AAh
Load Data 90h
to
Address 555h
Enter Product
Identification
Mode (1,2)
Load Data 55h
to
Address 2AAh
Load Data F0h
to
Address XXXh
or
Load Data F0h
to
Address 555h
Exit Product
Identification
Mode (3)
Exit Product
Identification
Mode (3)
Notes:
1. The device will enter Product Identification mode after excuting the Product ID Entry command.
2. Under Product Identification mode, the Manufacturer ID and Device ID of devices can be read at address
X0000h and X0001h where X = Don’t Care.
3. The device returns to standby operation.
Chart 3. Software Product Identification Entry/Exit Flowchart
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IS39LV040.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS39LV040 | 3.0 Volt-only CMOS Flash Memory | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |