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IS42S16100F 데이터시트 PDF




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부품번호 IS42S16100F 기능
기능 512K Words x 16 Bits x 2 Banks 16Mb SDRAM
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IS42S16100F 데이터시트, 핀배열, 회로
IS42/45S16100F, IS42VS16100F
512K Words x 16 Bits x 2 Banks
16Mb SDRAM
JUNE 2012
FEATURES
• Clock frequency:
IS42/45S16100F: 200, 166, 143 MHz
IS42VS16100F: 133, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single power supply:
IS42/45S16100F: Vdd/Vddq = 3.3V
IS42VS16100F: Vdd/Vddq = 1.8V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages 400-mil 50-pin TSOP-II and 60-ball
BGA
• Lead-free package option
• Available in Industrial Temperature
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100F,
IS45S16100F and IS42VS16100F are each organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All
inputs and outputs signals refer to the rising edge of the
clock input.
ADDRESS TABLE
Parameter
Power Supply Vdd/Vddq
Refresh Count
Row Addressing
IS42/45S16100F IS42VS16100F
3.3V
1.8V
2K/32ms
2K/32ms
A0-A10
Column Addressing
Bank Addressing
Precharge Addressing
A0-A7
A11
A10
KEY TIMING PARAMETERS
Parameter
CLK Cycle Time
-5(1) -6(2) -7 (2) -75 (3) -10 (3) Unit
CAS Latency = 3 5 6 7 7.5 10 ns
CAS Latency = 2 10 10 10 10 12 ns
CLK Frequency
CAS Latency = 3 200 166 143 133 100 Mhz
CAS Latency = 2 100 100 100 100 83 Mhz
Access Time from
Clock
CAS Latency = 3
5 5.5 5.5 6
7 ns
CAS Latency = 2 6 6 6 8 8 ns
Notes:
1. Available for IS42S16100F only
2. Available for IS42S16100F and IS45S16100F only
3. Available for IS42VS16100F only
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
1




IS42S16100F pdf, 반도체, 판매, 대치품
IS42/45S16100F, IS42VS16100F
PIN FUNCTIONS
Pin No. Symbol
20 to 24
27 to 32
A0-A10
Type
Input Pin
19
16
34
A11 Input Pin
CAS Input Pin
CKE Input Pin
35
18
CLK Input Pin
CS Input Pin
2, 3, 5, 6, 8, 9, 11 DQ0 to
12, 39, 40, 42, 43, DQ15
45, 46, 48, 49
14, 36
LDQM,
UDQM
DQ Pin
Input Pin
17
RAS Input Pin
15
WE Input Pin
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
VDDQ
VDD
VSSQ
VSS
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOW during precharge command, the bank selected by A11 is precharged, but if A10 is
HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
These signals become part of the OP CODE during mode register set command input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register set
command input.
CAS, in conjunction with the RAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When is
CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend
mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device are
acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When
LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot
be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the “Command
Truth Table” item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the “Command
Truth Table” item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSS is the device internal ground.
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
06/13/2012

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IS42S16100F 전자부품, 판매, 대치품
IS42/45S16100F, IS42VS16100F
IS42S16100F and IS45S16100F DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition -5 -6 -7 Unit
Icc1
Operating Current(1,2)
One Bank Operation, CAS Latency = 3 Com. 120 110 100 mA
Burst Length=1
Ind., A1 — 120 110 mA
trc trc (min)
Iout = 0mA
Icc2p
Precharge Standby Current CKE Vil (max) tck = tck (min) 2 2
(In Power-Down Mode)
2 mA
Icc2ps
Precharge Standby Current CKE Vil (max) tck = 2 2 2 mA
(In Power-Down and
CLK Vil (max)
Clock Suspend Mode)
Icc2n
Icc2ns
Precharge Standby Current(3) CKE Vih (min) tck = tck (min)
(In Non Power-Down Mode) CS Vih (min)
35 35 35 mA
Precharge Standby Current CKE Vih (min) tck =
20 20 20 mA
(In Non Power-Down and CLK Vil (max) Inputs are stable
Clock Suspend Mode)
Icc3P Active Standby Current CKE Vil (max) tck = tck (min) 3 3 3 mA
(In Power-Down Mode)
Icc3Ps
Active Standby Current
(In Power-Down and
Clock Suspend Mode)
CKE Vil (max) tck =
3 3 3 mA
CLK Vil (max) Inputs are stable
Icc3n
Active Standby Current(3) CKE Vih (min) tck = tck (min)
(In Non Power-Down Mode) CS Vih (min)
55 55 55 mA
Icc3ns
Active Standby Current CKE Vih (min) tck =
30 30 30 mA
(In Non Power-Down and CLK Vil (max) Inputs are stable
Clock Suspend Mode)
Icc4
Operating Current
(In Burst Mode)(1,3)
Both Banks activated tck = tck (min) 120 110 100 mA
Page Burst
Iout = 0mA
Icc5 Auto-Refresh Current
trc = trc (min)
Com. 120 100 80 mA
Ind., A1 — 110 90 mA
Icc6 Self-Refresh Current
CKE 0.2V 2 2 2 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and Vss for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
3. Inputs changed once every two clocks.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
06/13/2012
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