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PDF IS42VS16100F Data sheet ( Hoja de datos )
| Número de pieza | IS42VS16100F | |
| Descripción | 512K Words x 16 Bits x 2 Banks 16Mb SDRAM | |
| Fabricantes | ISSI | |
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IS42/45S16100F, IS42VS16100F
512K Words x 16 Bits x 2 Banks
16Mb SDRAM
JUNE 2012
FEATURES
• Clock frequency:
IS42/45S16100F: 200, 166, 143 MHz
IS42VS16100F: 133, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single power supply:
IS42/45S16100F: Vdd/Vddq = 3.3V
IS42VS16100F: Vdd/Vddq = 1.8V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages 400-mil 50-pin TSOP-II and 60-ball
BGA
• Lead-free package option
• Available in Industrial Temperature
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100F,
IS45S16100F and IS42VS16100F are each organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All
inputs and outputs signals refer to the rising edge of the
clock input.
ADDRESS TABLE
Parameter
Power Supply Vdd/Vddq
Refresh Count
Row Addressing
IS42/45S16100F IS42VS16100F
3.3V
1.8V
2K/32ms
2K/32ms
A0-A10
Column Addressing
Bank Addressing
Precharge Addressing
A0-A7
A11
A10
KEY TIMING PARAMETERS
Parameter
CLK Cycle Time
-5(1) -6(2) -7 (2) -75 (3) -10 (3) Unit
CAS Latency = 3 5 6 7 7.5 10 ns
CAS Latency = 2 10 10 10 10 12 ns
CLK Frequency
CAS Latency = 3 200 166 143 133 100 Mhz
CAS Latency = 2 100 100 100 100 83 Mhz
Access Time from
Clock
CAS Latency = 3
5 5.5 5.5 6
7 ns
CAS Latency = 2 6 6 6 8 8 ns
Notes:
1. Available for IS42S16100F only
2. Available for IS42S16100F and IS45S16100F only
3. Available for IS42VS16100F only
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
1
1 page  
IS42/45S16100F, IS42VS16100F
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS COMMAND
RAS DECODER
CAS &
WE CLOCK
A11 GENERATOR
MODE
REGISTER
11
A10
A9
REFRESH
SELF
A8
CONTROLLER
REFRESH
A7 CONTROLLER
A6
A5
A4
REFRESH
COUNTER
A3
A2
A1
A0
ROW
ADDRESS
11 LATCH
ROW
ADDRESS
BUFFER
11
11
MEMORY CELL
ARRAY
2048
BANK 0
SENSE AMP I/O GATE
256
8
COLUMN DECODER
8 256
SENSE AMP I/O GATE
ROW
ADDRESS
11 BUFFER
11
MEMORY CELL
2048 ARRAY
BANK 1
DATA IN
BUFFER
16 16
DQM
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
VSS/VSSQ
S16BLK.eps
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
5
5 Page 
IS42/45S16100F, IS42VS16100F
IS42VS16100F DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
-75 -10 Unit
Icc1
Operating Current(1,2)
One Bank Operation, CAS Latency = 3 45 35
Burst Length=1
mA
mA
trc ≥ trc (min)
CAS Latency = 2 50
Iout = 0mA
40
mA
Icc2p
Precharge Standby Current CKE ≤ Vil (max)
(In Power-Down Mode)
tck = tck (min) 0.3 0.3
mA
Icc2ps
Precharge Standby Current CKE ≤ Vil (max)
tck = ∞ 0.3 0.3
mA
(In Power-Down and
CLK ≤ Vil (max)
Clock Suspend Mode)
Icc2n
Precharge Standby Current(3) CKE ≥ Vih (min)
tck = tck (min) 25
(In Non Power-Down Mode) CS ≥ Vih (min)
20
mA
Icc2ns
Precharge Standby Current CKE ≥ Vih (min)
tck = ∞
10 10
mA
(In Non Power-Down and CLK ≤ Vil (max)
Inputs are stable
Clock Suspend Mode)
Icc3P
Active Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max)
tck = tck (min)
3
3
mA
Icc3Ps
Active Standby Current CKE ≤ Vil (max)
(In Power-Down and
CLK ≤ Vil (max)
Clock Suspend Mode)
tck = ∞
3
3
mA
Inputs are stable
Icc3n
Active Standby Current(3) CKE ≥ Vih (min)
(In Non Power-Down Mode) CS ≥ Vih (min)
tck = tck (min) 30 25
mA
Icc3ns
Active Standby Current CKE ≥ Vih (min)
tck = ∞
10 10
mA
(In Non Power-Down and CLK ≤ Vil (max)
Inputs are stable
Clock Suspend Mode)
Icc4
Operating Current
(In Burst Mode)(1,3)
Both Banks activated tck = tck (min) 60 50
Page Burst
mA
mA
Iout = 0mA
Icc5 Auto-Refresh Current
trc = trc (min)
50 40
mA
Icc6 Self-Refresh Current
CKE ≤ 0.2V 180 180
µA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and Vss for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
3. Inputs changed once every two clocks.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS42VS16100F.PDF ] | |
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