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기능 256-MBIT SYNCHRONOUS DRAM
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IS45R16160D 데이터시트, 핀배열, 회로
IS42R83200D, IS42R16160D
IS45R83200D, IS45R16160D
32Meg x 8, 16Meg x16
256-MBIT SYNCHRONOUS DRAM
MARCH 2010
FEATURES
• Clock frequency: 133, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 2.5V + 0.2V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 16 ms (A2 grade) or
64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II (x8 and x16)
54-ball BGA (x16 only)
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42/45R83200D IS42/45R16160D
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-75
7.5
10
133
100
5.4
6
Unit
ns
ns
Mhz
Mhz
ns
ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/16ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/16ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/02/2010
1




IS45R16160D pdf, 반도체, 판매, 대치품
IS42R83200D, IS42R16160D
IS45R83200D, IS45R16160D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 DQMH
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
PIN DESCRIPTIONS
A0-A12
Row Address Input
A0-A8
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ15 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
DQML
DQMH
Vdd
Vss
Vddq
Vssq
NC
Write Enable
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/02/2010

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IS45R16160D 전자부품, 판매, 대치품
IS42R83200D, IS42R16160D
IS45R83200D, IS45R16160D
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs A0-
A9 (x8); A0-A8 (x16) provides the starting column location.
When A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on
the DQM inputs two clocks earlier. When a given DQM
signal was registered HIGH, the corresponding DQ’s will
be High-Z two clocks later. DQ’s will provide valid data
when the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A9
(x8); A0-A8 (x16). Whether or not AUTO-PRECHARGE is
used is determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bisatnhke(sp)eirsioedxerecquuteirdedafftoerrbpaansksapgreecohfatrhgeinpge. r iOodnctReP,awbhaicnhk
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enable the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation.  Thestipulatedperiod(trc) is
required for a single refresh operation, and no other com-
mands can be executed during this period.  This command
is executed at least 8192 times for every Tref. During an
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A12. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A12 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/02/2010
7

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IS45R16160D

256-MBIT SYNCHRONOUS DRAM

ISSI
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