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IS43DR16320D 데이터시트 PDF




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기능 DDR2 DRAM
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IS43DR16320D 데이터시트, 핀배열, 회로
IS43/46DR86400D
IS43/46DR16320D
64Mx8, 32Mx16 DDR2 DRAM
FEATURES
Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers
per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions
with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6
supported
Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and
reduced strength options
On-die termination (ODT)
APRIL 2014
DESCRIPTION
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
64M x 8
16M x 8 x 4
banks
8K/64ms
32M x 16
8M x 16 x 4
banks
8K/64ms
Row Addressing
Column
Addressing
Bank Addressing
16K (A0-A13) 8K (A0-A12)
1K (A0-A9) 1K (A0-A9)
BA0, BA1
BA0, BA1
Precharge
Addressing
A10
A10
OPTIONS
Configuration(s):
64Mx8 (16Mx8x4 banks) IS43/46DR86400D
32Mx16 (8Mx16x4 banks) IS43/46DR16320D
Package:
x8: 60-ball BGA (8mm x 10.5mm)
x16: 84-ball WBGA (8mm x 12.5mm)
Timing – Cycle time
2.5ns @CL=5 DDR2-800D
2.5ns @CL=6 DDR2-800E
3.0ns @CL=5 DDR2-667D
3.75ns @CL=4 DDR2-533C
5ns @CL=3 DDR2-400B
Temperature Range:
Commercial (0°C Tc 85°C)
Industrial (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A1 (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A2 (-40°C Tc; Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
KEY TIMING PARAMETERS
Speed Grade -25D -3D
tRCD
12.5 15
tRP 12.5 15
tRC 55 55
tRAS
40 40
tCK @CL=3
55
tCK @CL=4
3.75 3.75
tCK @CL=5
2.5 3
tCK @CL=6
2.5 —
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
4/21/2014




IS43DR16320D pdf, 반도체, 판매, 대치품
IS43/46DR86400D, IS43/46DR16320D
Symbol
DQ0-7 x8
DQ0-15 x16
DQS, (DQS)
RDQS, (RDQS) x8
UDQS, (UDQS),
LDQS, (LDQS) x16
Type
Input/
Output
Input/
Output
Function
Data Input/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobes DQS(n) may be used in single ended mode
or paired with optional complementary signals DQS(n) to provide differential pair
signaling to the system during both reads and writes. A control bit at EMR(1)[A10]
enables or disables all complementary data strobe signals.
x8
DQS corresponds to the data on DQ0-DQ7
RDQS corresponds to the Read data on DQ0-DQ7, and is enabled by EMRS
command to EMR(1) [A11].
NC
VDDQ
VSSQ
VDDL
VSSDL
VDD
VSS
VREF
Supply
Supply
Supply
Supply
Supply
Supply
Supply
x16
LDQS corresponds to the data on DQ0-DQ7
UDQS corresponds to the data on DQ8-DQ15
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8 V +/- 0.1 V
DQ Ground
DLL Power Supply: 1.8 V +/- 0.1 V
DLL Ground
Power Supply: 1.8 V +/- 0.1 V
Ground
Reference voltage
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
4/21/2014

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IS43DR16320D 전자부품, 판매, 대치품
IS43/46DR86400D, IS43/46DR16320D
electrical specifications
Absolute Maximum DC Ratings
Symbol
Vdd
Vddq
Vddl
Vin, Vout
Tstg
Ii
Ioz
Ivref
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Input Leakage Current
Output Leakage Current
Uref Leakage Current
Rating
- 1.0~ 2.3
- 0.5~ 2.3
- 0.5~ 2.3
- 0.5~ 2.3
-55 to +150
- 5~ 5
- 5~ 5
- 2~ 2
Units
V
V
V
V
°C
uA
uA
uA
Notes
1,3
1,3
1,3
1,4
1, 2
4
4
3
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and
VDDL are less than 500 mV, Vref may be equal to or less than 300 mV.
4. Voltage on any input or I/O may not exceed voltage on VDDQ.
AC & DC Recommended Operating Conditions
Recommended DC Operating Conditions (SSTL-1.8)
Symbol Parameter
Rating
Units Notes
Min.
Typ.
Max.
VDD
Supply Voltage
1.7 1.8 1.9 V 1
VDDL Supply Voltage for DLL
1.7
1.8
1.9 V 5
VDDQ Supply Voltage for Output
1.7
1.8
1.9 V 1, 5
VREF
Input Reference Voltage
0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2. 3
VTT Termination Voltage
VREF - 0.04
VREF
VREF + 0.04 V 4
Notes:
1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less than
or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be
about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak ac noise on VREF may not exceed +/-2 % VREF(dc).
4. VTT of transmitting device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. A
4/21/2014

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