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부품번호 | SN74LS256 기능 |
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기능 | DUAL 4-BIT ADDRESSABLE LATCH | ||
제조업체 | Motorola Semiconductors | ||
로고 | |||
전체 6 페이지수
DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A0, A1), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q0 – Q3).
When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs
(Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and
E are both LOW. When CL is HIGH and E is LOW, the selected output
(Q0 – Q3), determined by the Address inputs, follows D. When the E goes
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address
(A0, A1) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E= CL = HIGH).
• Serial-to-Parallel Capability
• Output From Each Storage Bit Available
• Random (Addressable) Data Entry
• Easily Expandable
• Active Low Common Clear
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CL E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
12
A0 A1
3 4 56 78
Da Q0a Q1a Q2a Q3a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Da, Db
E
Address Inputs
Data Inputs
Enable Input (Active LOW)
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
CL Clear Input (Active LOW)
0.5 U.L.
0.25 U.L.
Q0a – Q3a,
Q0b – Q3b
Parallel Latch Outputs (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3
2 1 15
14 13
Da E
A0
A1
CL
Q0a Q1a Q2a Q3a
A0 E Db
A1
CL
Q0b Q1b Q2b Q3b
4 56 7
9 10 11 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-421
SN54 / 74LS256
AC SET-UP REQUIREMENTS (TA = 25°C)
Symbol
ts
ts
th
th
tW
Parameter
Data Setup Time
Address Setup Time
Data Hold Time
Address Hold Time
Enable Pulse Width
Limits
Min Typ Max
20
0
0
15
15
Unit
ns
ns
ns
ns
ns
Test Conditions
Figures 4 & 6
Figure 4
Figure 6
Figure 1
VCC = 5.0 V
AC WAVEFORMS
D
tpw
E
tPHL
Q
tpw
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: CL = H, A = STABLE
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
D
1.3 V
1.3 V
tPHL
tPLH
Q
1.3 V
1.3 V
OTHER CONDITIONS: E = L, CL = H, A = STABLE
Figure 2. Turn-on and Turn-off Delays,
Data to Output
A1 1.3 V
1.3 V
A1
Q1
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: E = L, CL = L, D = H
Figure 3. Turn-on and Turn-off Delays,
Address to Output
D
th(H)
th(L)
ts(H)
E
ts(L)
1.3 V
Q=D
Q
Q=D
OTHER CONDITIONS: C = H, A = STABLE
Figure 4. Setup and Hold Time, Data to Enable
C 1.3 V
tPHL
1.3 V
Q
OTHER CONDITIONS: E = H
Figure 5. Turn-on Delay, Clear to Output
A 1.3 V STABLE ADDRESS
ts th
E 1.3 V
OTHER CONDITIONS: CL = H
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
FAST AND LS TTL DATA
5-424
4페이지 | |||
구 성 | 총 6 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
SN74LS251 | Data Selectors/Multiplexers With 3-State Outputs | Texas Instruments |
SN74LS251 | LOW POWER SCHOTTKY | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |