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PDF 54FCT574 Data sheet ( Hoja de datos )
| Número de pieza | 54FCT574 | |
| Descripción | Octal D-Type Flip-Flop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1999
54FCT574
Octal D-Type Flip-Flop with TRI-STATE® Outputs
General Description
The ’FCT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE). The
information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ’FCT374 except for
the pinouts.
Features
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’FCT374
n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 32 mA, source capability of
12 mA
n TTL input and output level compatible
n CMOS power consumption
n Standard Microcircuit Drawing (SMD) 5962-8951301
Ordering Code
Military
54FCT574DMQB
54FCT574FMQB
54FCT574LMQB
Package Number
J20A
W20A
E20A
Connection Diagrams
Pin Assignment for DIP and Flatpak
Package Description
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Pin Descriptions
Pin
Names
D0– D7
CP
OE
O0– O7
Description
Data Inputs
Clock Pulse Input
(Active Rising Edge)
TRI-STATE Output Enable
Input (Active LOW)
TRI-STATE Outputs
DS100966-1
Pin Assignment
for LCC
DS100966-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100966
www.national.com
1 page  
AC Loading
DS100966-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. VM = 1.5V
DS100966-6
Input Pulse Requirements
Amplitude Rep. Rate
tw
3.0V
1 MHz 500 ns
tr
2.5 ns
tf
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100966-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100966-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100966-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
5
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
DS100966-9
www.national.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 54FCT574.PDF ] | |
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