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PDF PIC18F26K40 Data sheet ( Hoja de datos )
| Número de pieza | PIC18F26K40 | |
| Descripción | Memory Programming Specification | |
| Fabricantes | Microchip | |
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PIC18(L)F2X/4XK40
PIC18(L)F2X/4XK40 Memory Programming Specification
1.0 OVERVIEW
This programming specification describes an SPI-based programming method for the PIC18(L)F2X/4XK40 family of
microcontrollers. Section 3.0 “Programming Algorithms” describes the programming commands, programming
algorithms and electrical specifications which are used in that particular programming method. Appendix B contains
individual part numbers, device identification and checksum values, pinout and packaging information and Configuration
Words.
Note 1: This is a SPI-compatible programming method with 8-bit commands.
2: The low-voltage entry code is now 32 clocks and MSb first, unlike previous PIC18 devices which had 33
clocks and LSb first.
1.1 Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data Flash Memory (EEPROM), dedicated “user ID” locations and
the Configuration Words.
1.2 Write and/or Erase Selection
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document related to erasing/writing to the program memory are defined in Table 1-1 and are detailed below.
TABLE 1-1: PROGRAMMING TERMS
Term
Definition
Programmed Cell
Erased Cell
Erase
Write
Program
A memory cell at logic ‘0’
A memory cell at logic ‘1’
Change memory cell from a ‘0’ to a ‘1’
Change memory cell from a ‘1’ to a ‘0’
Generic erase and/or write
1.2.1 ERASING MEMORY
Memory is erased by row or in bulk, where ‘bulk’ includes many subsets of the total memory space. The duration of the
erase is determined by the size of program memory. All Bulk ICSP Erase commands have minimum VDD requirements,
which are higher than the Row Erase and write requirements.
1.2.2 WRITING MEMORY
Memory is written one row at a time. Multiple Load Data for NVM commands are used to fill the row data latches. The
duration of the write can be determined either internally or externally.
1.2.3 MULTI-WORD PROGRAMMING INTERFACE
Program Flash Memory (PFM) panels include up to a 64-word (one row) programming interface. Refer to Table 3-3 for
row size of erase and write operations for the PIC18(L)F2X/4XK40 family. The row to be programmed must first be
erased either with a Bulk Erase or a Row Erase.
2014 Microchip Technology Inc.
DS40001772A-page 1
1 page  
PIC18(L)F2X/4XK40
2.1 User ID Location
A user may store identification information (user ID) in eight designated locations. The user ID locations are mapped to
20 0000h-20 000Fh. Each location is 16 bits in length. It is recommended that the Most Significant nibble of each ID be
Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. Code
protection has no effect on these memory locations. Each location may be read with code protection enabled or
disabled.
2.2 Device/Revision ID
The 16-bit device ID word is located at 3F FFFEh and the 16-bit revision ID is located at 3F FFFCh. These locations are
read-only and cannot be erased or modified.
REGISTER 2-1: DEVICEID: DEVICE ID REGISTER
R R R RR
DEV15
bit 15
DEV14
DEV13
DEV12
DEV11
R
DEV10
R
DEV9
R
DEV8
bit 8
R
DEV7
bit 7
R
DEV6
R
DEV5
R
DEV4
R
DEV3
R
DEV2
R
DEV1
R
DEV0
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-0
DEV<15:0>: Device ID bits
REGISTER 2-2:
R
1
bit 15
REVISIONID: REVISION ID REGISTER
R R RR
0 10
RR
MJRREV<5:2>
R
bit 8
RR
MJRREV<1:0>
bit 7
R RR R R R
MNRREV<5:0>
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-6
bit 5-0
Read as ‘1010’
These bits are fixed with value ‘1010’ for all devices in this programming specification.
MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by an all layer revision
(A0, B0, C0, etc...).
Revision A = 6’b00_0000
MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.
Revision A0 = 6’b00_0000
2014 Microchip Technology Inc.
DS40001772A-page 5
5 Page 
PIC18(L)F2X/4XK40
Note:
All clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host
programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is a
bidirectional data line. For all commands and payload fields, except the Read Data from NVM payload, the
host programming device continuously drives the ICSPDAT line. Both the host programmer device and the
microcontroller should latch received ICSPDAT values on the falling edge of the ICSPCLK line. When the
microcontroller receives ICSPDAT line values from the host programmer, the ICSPDAT values must be
valid a minimum of TDS before the falling edges of ICSPCLK and should remain valid for a minimum of TDH
after the falling edge of ICSPDAT. See Figure 3-5.
FIGURE 3-5:
CLOCK AND DATA TIMING
TCKH TCKL
ICSPCLK
ICSPDAT
as
input
ICSPDAT
as
output
TDS TDH
TCO
TLZD
ICSPDAT
from input
to output
ICSPDAT
from output
to input
THZD
3.1.3.1 Load Data for NVM
The Load Data for NVM command is used to load one programming data latch (for example, one 16-bit instruction word
for program memory/configuration memory/user ID memory, or one 8-bit data for an EEPROM data memory address).
The latched data is written into program or EEPROM memory after the Begin Internally Timed Programming or Begin
Externally Timed Programming command is issued (see Section 3.2 “Programming Algorithms”). The Load Data for
NVM command can be used to load data for Program Flash Memory (PFM) (see Figure 3-6) or the Data Flash Memory
(DFM) (see Figure 3-7). Depending on the value of bit 1 of the command, the PC may or may not be incremented (see
Table 3-1).
FIGURE 3-6:
LOAD DATA FOR NVM (PFM)
ICSPCLK
765
432 1 0
23 22
TDLY
17 16
10
TDLY
ICSPDAT
0 00 0 0 0 J0
8-Bit Command
00
Start Bit
0 MSb
LSb 0
Stop Bit
24-Bit Payload Field
2014 Microchip Technology Inc.
DS40001772A-page 11
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