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부품번호 | BLUENRG-1 기능 |
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기능 | Bluetooth low energy wireless system-on-chip | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 30 페이지수
BlueNRG-1
Bluetooth® low energy wireless system-on-chip
Datasheet - production data
WLCSP34
QFN32
Features
Bluetooth specification compliant master,
slave and multiple roles simultaneously,
single-mode Bluetooth low energy system-
on-chip
Operating supply voltage: from 1.7 to 3.6 V
Integrated linear regulator and DC-DC step-
down converter
Operating temperature range: -40 °C to 105
°C
High performance, ultra-low power Cortex-
M0 32-bit based architecture core
Programmable 160 KB Flash
24 KB RAM with retention (two 12 KB
banks)
1 x UART interface
1 x SPI interface
2 x I2C interface
14 or 15 GPIO
2 x multifunction timer
10-bit ADC
Watchdog & RTC
DMA controller
PDM stream processor
16 or 32 MHz crystal oscillator
32 kHz crystal oscillator
32 kHz ring oscillator
Battery voltage monitor and temperature
sensor
Up to +8 dBm available output power (at
antenna connector)
Excellent RF link budget (up to 96 dB)
Accurate RSSI to allow power control
8.2 mA maximum TX current (@ 0 dBm, 3.0
V)
Down to 1 µA current consumption with
active BLE stack (sleep mode)
Compliant with the following radio frequency
regulations: ETSI EN 300 328, EN 300 440,
FCC CFR47 Part 15, ARIB STD-T66
Pre-programmed bootloader via UART
QFN32, WCSP34 package option
Dedicated wettable flank QFN package for
automotive grade qualification
Applications
Automotive product
Watches
Fitness, wellness and sports
Consumer medical
Security/proximity
Remote control
Home and industrial automation
Assisted living
Mobile phone peripherals
Lighting
PC peripherals
Table 1: Device summary table
Order code
Package
Packing
BLUENRG-132
QFN32
(5 x 5 mm)
Tape and reel
BLUENRG-134
WLCSP34
Tape and reel
BLUENRG-132Y
QFN32
(5 x 5 mm)
Automotive
grade Level
Tape and reel
June 2016
DocID028866 Rev 1
This is information on a product in full production.
1/173
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Contents
BlueNRG-1
8 General characteristics............................................................... 155
9 Electrical specification................................................................ 156
9.1 Electrical characteristics................................................................ 156
9.1.1 Peripheral current consumption ..................................................... 157
9.2 RF general characteristics ............................................................ 157
9.3 RF transmitter characteristics........................................................ 158
9.4 RF receiver characteristics............................................................ 158
9.5 High speed crystal oscillator characteristics.................................. 160
9.5.1 High speed crystal oscillator........................................................... 161
9.6 Low speed crystal oscillator characteristics .................................. 162
9.7 High speed ring oscillator characteristics ...................................... 162
9.8 Low speed ring oscillator characteristics ....................................... 162
9.9 N-fractional frequency synthesizer characteristics ........................ 162
9.10 Auxiliary blocks characteristics...................................................... 163
10 Package information ................................................................... 165
10.1 QFN32 package information ......................................................... 166
10.2 WLCSP34 package information .................................................... 168
11 PCB assembly guidelines ........................................................... 170
12 Revision history .......................................................................... 172
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4페이지 BlueNRG-1
List of tables
Table 96: I2C - SR register description: address offset I2CX_BASE_ADDR+0x14 .................................89
Table 97: I2C - RFR register description: address offset I2CX_BASE_ADDR+0x18 ..............................91
Table 98: I2C - TFTR register description: address offset I2CX_BASE_ADDR+0x1C ............................91
Table 99: I2C - RFTR register description: address offset I2CX_BASE_ADDR+0x20 ............................91
Table 100: I2C - DMAR register description: address offset I2CX_BASE_ADDR+0x24 .........................91
Table 101: I2C - BRCR register description: address offset I2CX_BASE_ADDR+0x28..........................92
Table 102: I2C - IMSCR register description: address offset I2CX_BASE_ADDR+0x2C .......................92
Table 103: I2C - RISR register description: address offset I2CX_BASE_ADDR+0x30. ..........................94
Table 104: I2C - MISR register description: address offset I2CX_BASE_ADDR+0x34...........................97
Table 105: I2C - ICR register description: address offset I2CX_BASE_ADDR+0x38..............................99
Table 106: I2C - THDDAT register description: address offset I2CX_BASE_ADDR+0x4C ..................100
Table 107: I2C - THDSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x50 .100
Table 108: I2C - TSUSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x58 .100
Table 109: Flash commands ..................................................................................................................104
Table 110: Flash interface timing............................................................................................................104
Table 111: FLASH controller registers....................................................................................................104
Table 112: FLASH – COMMAND register description: address offset FLASH_BASE_ADDR+0x00 ....105
Table 113: FLASH – CONFIG register description: address offset FLASH_BASE_ADDR+0x04 .........105
Table 114: FLASH - IRQSTAT register description: address offset FLASH_BASE_ADDR+0x08 ........105
Table 115: FLASH - IRQMASK register description: address offset FLASH_BASE_ADDR+0x0C .......106
Table 116: FLASH - IRQRAW register description: address offset FLASH_BASE_ADDR+0x10 .........106
Table 117: FLASH – SIZE register description: address offset FLASH_BASE_ADDR+0x14 ...............106
Table 118: FLASH – ADDRESS register description: address offset FLASH_BASE_ADDR+0x18 ......106
Table 119: FLASH – LFSRVAL register description: address offset FLASH_BASE_ADDR+0x24 .......106
Table 120: FLASH – TIMETRIM1 register description: address offset FLASH_BASE_ADDR+0x28 ....106
Table 121: FLASH – TIMETRIM2 register description: address offset FLASH_BASE_ADDR+0x2C ...107
Table 122: FLASH – TIMETRIM3 register description: address offset FLASH_BASE_ADDR+0x30 ....107
Table 123: FLASH – DATA0 register description: address offset FLASH_BASE_ADDR+0x40............107
Table 124: FLASH – DATA1 register description: address offset FLASH_BASE_ADDR+0x44............107
Table 125: FLASH – DATA2 register description: address offset FLASH_BASE_ADDR+0x48............107
Table 126: FLASH – DATA3 register description: address offset FLASH_BASE_ADDR+0x4C ...........107
Table 127: IO functional map..................................................................................................................108
Table 128: GPIO interrupt modes...........................................................................................................109
Table 129: Pin characteristics.................................................................................................................109
Table 130: IO pull values ........................................................................................................................109
Table 131: GPIO registers ......................................................................................................................111
Table 132: GPIO – DATA register description: address offset GPIO_BASE_ADDR+0x00 ...................112
Table 133: GPIO – OEN register description: address offset GPIO_BASE_ADDR+0x04.....................112
Table 134: GPIO – PE register description: address offset GPIO_BASE_ADDR+0x08........................112
Table 135: GPIO – DS register description: address offset GPIO_BASE_ADDR+0x0C .......................112
Table 136: GPIO – IS register description: address offset GPIO_BASE_ADDR+0x10 .........................113
Table 137: GPIO – IBE register description: address offset GPIO_BASE_ADDR+0x14.......................113
Table 138: GPIO – IEV register description: address offset GPIO_BASE_ADDR+0x18.......................113
Table 139: GPIO – IE register description: address offset GPIO_BASE_ADDR+0x1C.........................113
Table 140: GPIO – MIS register description: address offset GPIO_BASE_ADDR+0x24 ......................113
Table 141: GPIO – IC register description: address offset GPIO_BASE_ADDR+0x28 .........................113
Table 142: GPIO - MODE0 register description: address offset GPIO_BASE_ADDR+0x2C ................113
Table 143: GPIO – MODE1 register description: address offset GPIO_BASE_ADDR+0x30................114
Table 144: GPIO – DATS register description: address offset GPIO_BASE_ADDR+0x3C ..................114
Table 145: GPIO – DATC register description: address offset GPIO_BASE_ADDR+0x40...................115
Table 146: GPIO - MFTX register description: address offset GPIO_BASE_ADDR+0x44....................115
Table 147: MFT modes...........................................................................................................................116
Table 148: MFT IO functions ..................................................................................................................124
Table 149: MFT interrupt functions .........................................................................................................125
Table 150: MFTX registers .....................................................................................................................126
Table 151: MFTX – TNCNT1 register description: address offset MFTX_BASE_ADDR+0x00.............126
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부품번호 | 상세설명 및 기능 | 제조사 |
BLUENRG-1 | Bluetooth low energy wireless system-on-chip | STMicroelectronics |
BLUENRG-132 | Bluetooth low energy wireless system-on-chip | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |